Gate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.