Single wafer rapid thermal processing (RTP) is emerging as a key player in the processing of advanced sub-half micron memory devices. The high temperature processing of large diameter silicon wafers can create sufficient thermal stress for generation of dislocation, slip, and gross mechanical instability of the wafer. The aforementioned factors may lead to loss of device yield, dielectric defects, and reduced photolithographic yield due to degradation of virtual wafer flatness. Moreover, the loss of geometrical planarity of wafer due to warpage can make it impossible to process a wafer or can lead to self-fracture of the wafer.
In this paper we present the warpage and stress results of our study on plain and patterned structures that were subjected to RTP at different stages of the CMOS process flow. Experimental results have been gathered with full wafer scanning technology using non-contact capacitive probes to measure more accurate global stress values. The stress and warpage values on the patterned wafers could be measured accurately without any light scattering effects and destructive interference. It is reported that the thermal processing creates significant variations in shape change around the wafer which could be identified using the full wafer data set acquired using this evaluation technique. We have successfully tracked variations in film stress for both plain and patterned structures as a cumulative effect and correlated it with the overall wafer warpage. The effects of incoming wafer warpage, ramp rate in RTP, and high stress nitride films on the overall wafer warpage are also reported.