BST/TiO2/(Barrier Layer) stacked dielectric structure has been proposed for ultra thin (<20Å) gate dielectric application to overcome the direct tunneling current problem of Si02. To characterize the alternative dielectrics, MIM and MIS capacitors were fabricated. TiO2 is believed to prevent BST and Si from reaction and interdiffusion while TiC2 itself is stable due to the strong binding energy. For better interfacial quality of TiO2/Si interface, proper barrier layer is needed between TiO2 and Si. Optimization of this barrier layer was performed by RTP grown N20 oxide and self-grown interfacial oxide layer with various annealing conditions. To monitor these barrier layers, TEM and electrical analysis were performed. From TEM observation, it was found that interfacial layer was formed in every sample whether it was intentionally grown or not. It was observed that the leakage current of Pt/TiO2/Si dramatically increased after 700'C or higher temperature annealing. This might be related to the transition of crystal structure of TiO2 from anatese to rutile at about 700°C. It was also found that both Pt/BST/TiO2/Si and Pt/TiO2/Si showed lower leakage current compare to the conventional NO oxide at comparable equivalent SiO2 thickness. These results imply that these materials hold some promise as alternatives of pure SiO2 in very thin range.