For embedded DRAM (E-DRAM) devices with feature sizes of 0.25 µm and beyond, contact processes with low contact resistance and low junction leakage current are required. The contact etch process needs to etch through multi-layer structures with SiO2, SiON/SiN layers and stop on Ti-polycide gate and Ti-salicide active regions at the same time. The key issues include high selectivity to TiSix, vertical profile, complete removal of SiON/SiN cap layer and no polymer residues. In this paper, multi-layer contact etching without attacking TiSix is reported. Using new process chemistry, the new contact etch process has been demonstrated for the manufacturing of 0.25 µm E-DRAM and beyond.