Strained-Si based Field Effect Transistors (FETs) have enabled improvement of carrier transport in Metal Oxide Semiconductor (MOS)-based devices, both in the ON state of the device and in the sub-threshold region. This leads to devices with higher ratios of on-to-off current, improvements in the device sub-threshold slope, lower voltage operation, and carrier mobility enhancement. However, in order to understand the fundamental physics of these devices, it is important to address the stress conditions of the strained-Si channel layers after device processing, particularly after the ion-implantation process. In this work, we have studied Si+ self ion-implantation and thermally annealed strained-Si channel layers in n-MOSFETs. It has been observed that the density of defects in the strained-Si layer depends upon implant dose as well as thermal treatment. Using energy dispersive spectroscopy (EDS) spectra, it is found that Ge is present in the strained Si layer when analyzed after Si+ implantation and rapid thermal annealing. The presence of Ge in the strained Si channel layer causes relaxation of strain. This is verified by Convergent Beam Electron Diffraction (CBED) by measuring the lattice constant of the strained channel. It is concluded that electron mobility enhancements can be degraded in n- MOSFETs due to presence of both Ge up-diffusion and defects.