In this study, we design a differential CMOS power amplifier using a 180-nm SOI RFCMOS process for 802.11n (64-QAM, 20 MHz bandwidth, 9.6 dB peak to average power ratio (PAPR)) applications. To minimize the chip area and mismatch in differential signals, we propose a layout method with an inter-stage matching network using a split inductor. By virtue of the symmetrical layout of the proposed split inductor, the mismatch in the differential signals is minimized, while the interconnection lines between the driver and power stages are shortened to minimize the overall chip area and the loss induced by the resistive parasitic components. The designed power amplifier is measured using a wireless local area network (WLAN) 802.11n signal to verify the feasibility of the proposed layout technique. The power amplifier achieved 20.34 dBm output power, while the measured EVM for the 802.11n applications is satisfied. From the measured results, we successfully prove the feasibility of the proposed power amplifier.