Except for a few special cases, the electrical and optical properties of most III-V semiconductor surfaces and interfaces can be explained in terms of surface Fermi level pinning. However, despite years of research there is no universal agreement on the origin of this pinning. This problem is of more than just academic interest since pinning affects optoelectronic device performance via surface recombination losses, and high speed device performance through uncontrollable ohmic and Schottky contact properties for MESFETs and through a high interface trap density for MISFETs.
This talk reviews some of the approaches to the pinning problem and presents some recent results on the role of misfit dislocations in pinning. In particular it will be shown that there are are several models which can explain the usually observed pinning positions. However, we have developed a modified work function model capable of explaining both the usual pinning positions and the experimentally observed exceptions in Schottky barrier height for some metal/semiconductor interfaces. The electrical properties of lattice mismatched GaInAs/GaAs heterojunctions suggest that Fermi level pinning occurs at misfit dislocations.