In the present paper, we present a dynamic gate biasing technique applied to a 10 W, S-band GaN amplifier. The proposed methodology addresses class-B operation of power amplifiers that offers the potential for high efficiency but requires a careful attention to maintain good linearity performances at large output power back-off. This work proposes a solution to improve the linearity of class-B amplifiers driven by radio frequency-modulated signals having large peak to average power ratios. An important aspect of this work concerns the characterization of the dynamic behavior of GaN devices for gate bias trajectory optimization. For that purpose, the experimental study reported here is based on the use of a time-domain envelope setup. A specific gate bias circuit has been designed and connected to a 10 W – 2.5 GHz GaN amplifier demo board from CREE. Compared to conventional class-B operation with a fixed gate bias, a 10-dB improvement in terms of third-order intermodulation is reached. When applied to the amplification of 16-QAM signals the proposed technique demonstrates significant ACPR reduction of order of 6 dB along with error vector magnitude (EVM) improvements of five points over 8 dB output power back-off with a minor impact on power-added efficiency performances.