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We demonstrate the use of a synchrotron radiation source for in situ x-ray diffraction analysis during rapid thermal annealing (RTA) of 0.35 μm Salicide (self-aligned silicide) and 0.4 μm Polycide (silicided polysilicon) TiSi2 Complementary Metal Oxide Semiconductor (CMOS) gate structures. It is shown that the transformation from the C49 to C54 phase of TiSi2 occurs at higher temperatures in submicron gate structures than in unpatterned blanket films. In addition, the C54 that forms in submicron structures is (040) oriented, while the C54 that forms in unpatterned Salicide films is randomly oriented. Although the preferred oreintation of the initial C49 phase was different in the Salicide and Polycide gate structures, the final orientation of the C54 phase formed was the same. An incomplete conversion of C49 into C54-TiSi2 during the RTA of Polycide gate structures was observed and is attributed to the retarding effects of phosphorus on the transition.
The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.
We report on a study of the effects of dopant concentration and linewidth on the formation of TiSi2 on polysilicon. The transformation from the C49 phase to the C54 phase is inhibited by a high concentration of either phosphorus or arsenic in blanket polysilicon films. For sub-half-micron lines, patterned in polysilicon doped with As or P, agglomeration is the key factor in the inability to produce low resistance silicide. The result is a critically shrinking process window for the attainment of low resistance VLSI interconnects.
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