Inverted-staggered a-Si:H TFT was prepared by successive PECVD of a- SiN1.7:H and a- Si:H layers. Drain current ID vs gate voltage VG characteristics of the TFT were investigated. The gate-voltage swing defined by S=dVG/d(log ID) in the subthreshold region was 1.4 V at room temperature. If the observed S value is attributed to the bulk gap state density, the space- charge layer width is estimated to be about 450 A. This value is too small compared with the a-Si:H layer width of about 3000 A in the TFT, which exhibits good performance. On the other hand, if the S value is attributed to the interface states, a state density of 1.5×l012 (cm2 eV)-1 is necessary. Nearly the same density, (l-2)xl012 (cm2 eV)-1, nearly independent of the energy level, was obtained in oura-SiN1.7:H/c-Si interface by capacitance measurements. Therefore, it is concluded that the interface states are the main origin of the subthreshold characteristics in our a-Si:H TFT.