A 32 Mbit chain FeRAM™ stack with 0.20μm minimum feature size was etched with two subsequent lithography/RIE steps: in mask step 1 the platinum/SRO (strontium ruthenium oxide) top electrode and the PZT (lead zirconate titanate) layer, in mask step 2 the bottom electrode together with the Ir/IrO2 diffusion barrier were etched. The stack was etched with various chlorine based chemistries. High temperature etching processes were applied to suppress residues by the formation of volatile etching byproducts resulting in a highly anisotropic etching profile and low redeposition.
Profile angles of 75° for step 1 and 80° for step 2 could be achieved. For the thin SRO-layer a separate etching recipe was developed to avoid surface roughening caused by micromasking. The influence of etching temperature and different gas chemistries on the etching behavior was evaluated. Reliable end point detection and good uniformity of the individual etching processes were obtained, both being crucial for the application of a multi-step recipe. The ferroelectric properties of the capacitor were confirmed by hysteresis measurements. This demonstrates that the ferroelectric properties were conserved during RIE etch processes at high temperature.