We have investigated the shift of threshold voltage in the a-Si:H TFT due to the various negative pulse width stress. The drain bias dependent threshold voltage shift in the pulsed stress of a-Si:H TFT for AMOLED backplane is also measured and analyzed. When a positive gate and drain bias is applied to a-Si:H TFT (W/L = 200/4 Ým), VTH of a-Si:H TFT is increased during the stress time due to the defect state creation and charge trapping. VTH of a-Si:H TFT is increased from 1.645V to 2.53V (δVTH=0.885V) after the DC gate bias stress of VGS=15V, VDS=0V for 20,000sec. When the pulsed negative bias stress is applied to the gate electrode of the current driving a-Si:H TFT with the drain bias, VTH shift is considerably reduced due to the hole trapping into the gate insulator during the stress. When a negative pulse width is 16msec (pulse of 60Hz), the VTH is increased form 1.594V to 2.195V (δVTH=0.601V). When a negative pulse width increases from 16msec to 5sec without drain bias (VDS=0V), VTH is increased from 1.615V to 2.055V (δVTH=0.44V). When a drain bias is increased from 0V to 15V, VTH is slightly decreased from 1.58V to 1.529V (δVTH=-0.051V) due to large (-30V) VGD (VG=-15V, VD=15V) bias, while it is increased from 1.66V to 2.078V (δVTH=0.418V) width DC gate bias stress of VGS=15V, VDS=15V for 20,000sec.