We have fabricated Pr-based high-k gate dielectric films by physical vapor deposition of metallic Pr on SiO2 under ultra-high vacuum (UHV) conditions at room temperature, followed by oxidation and annealing steps. The films have been analyzed by electrical measurements, X-ray Photoelectron Spectroscopy (XPS) and Transmission Electron Microscopy (TEM). Some insight into the physical processes involved has been obtained from ab initio calculations. The high-k gate stacks consist of a SiO2-based buffer with an enhanced dielectric constant and a Pr silicate barrier with a high dielectric constant. The role of the buffer is to preserve the high quality of the SiO2/Si(001) interface, and the role of the barrier is to keep the tunneling currents low by increasing its physical thickness. A Pr film deposited on a 1.8 nm SiO2 layer, oxidized at room temperature by air, and annealed in N2 atmosphere with O2 partial pressure of 10−3 mbar results in a stack with the Capacitance Equivalent Thickness of 1.5 nm and leakage of 10−4 A/cm2.