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The purpose of this work was to investigate integration of aluminum multi-level damascene devices with the CMP module. Traditionally aluminum is used in the Metal-1 level of device manufacturing and Reverse Ion Etching (RIE) is used to remove the aluminum over layer. However for <0.25-µproportional]m device rules RIE is not a method of choice due to incomplete removal of the over layer leaving stringers that cause shorting, as well as poor With-In Wafer NonUniformity (WIWNU). The result is loss of device yield and process problems for BEOL modules. Integrating aluminum device wafers into the CMP module has its own drawbacks such as immature consumables, i.e., slurry and polishing pads, as well as ease of scratching the soft aluminum interconnect structures. Hence the basis of this work is to highlight the main issues that impede the integration of the aluminum CMP process. Specifically we investigated the origin of deep aluminum scratches and the effect of not completely removing the residue barrier material, which can cause shorting and poor electrical performance. It is argued in this work that the observed deep scratches in the aluminum material are due to the polished debris emanating from the titanium glue layer. Recommendations are made to help to reduce this effect by design modification to the die layout on the patterned wafer and using electrical testing methods to help ascertain the minimum Over Polishing (OP) time required in order to ensure maximum die yield.
The dependence of IC fabrication on the Chemical Mechanical Planarization (CMP) process increases as the device features go down to 0.25 micron or beyond. Due to the tighter CMP process spec, it is very important to reduce the within wafer non-uniformity (WIWNU%) to achieve higher process yield. The symmetrical increment of linear velocity at wafer edge is not sufficient to change wafer edge profile by breaking the matched speed rule. A better solution is through the change of head design for a fixed platen from the polisher design point of view. This study demonstrates the improvement of the CMP process performance, especially at the wafer edge, from the modification of the floating type polish head. The best WIWNU% from a single air chamber head is about 5.12% at 6-mm edge exclusion (EE). In order to obtain better pad deformation control, the retaining-ring pressure chamber is separated from that of the sub-carrier. The average WIWNU% is about 4% for 3-mm and 5-mm EE from two-pressure-chamber head. Due to the limitation of retaining-ring pressure effect, a third pressure chamber is further added that can be extended the edge control up to 1 inch from the wafer edge. The WIWNU% is about 3.8% at 5-mm edge exclusion with low down forces. The slurry and insert types also show effect on the wafer edge profile. It has been also proven that this three-pressure-chamber head is able to reduce the post-CMP thickness variation from the ILD production wafer, especially at wafer edges. More detailed information and CMP mechanism will be discussed in this paper.
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