In this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.