As was discussed in Chapter 1, the undoped planar FD/SOI UTB MOSFET with thin BOX and substrate ground plane (GP), illustrated in Fig. 1.3(b), is a primary candidate for future nanoscale CMOS, along with the quasi-planar (also FD) UTB FinFET. We discuss in this chapter the features of the FD/SOI MOSFET, with reference to the generic analyses in Chapter 2, emphasizing its scaling and performance potentials. Although the basic FD/SOI MOSFET, along with the PD/SOI MOSFET, has been under development since the 1980s, the thin-BOX focus materialized much later (Fenouillet-Beranger et al., 2009; Faynot et al., 2010; Liu et al., 2010), when the SOI technology matured to enable high-quality SOI wafers with BOX thicknesses scaled down to ~10 nm (Maleville, 2011). Early on, classical FD/SOI MOSFETs with thick BOX, shown in Fig. 1.3(a) and detailed in Fig. 3.1(a), were of much interest because of advantageous features such as near-ideal S and high Ion (Colinge, 1997), which originate from the (front) gate-substrate charge coupling enabled by the thin FD/SOI body on a thick BOX, as discussed in Chapter 2. However, for nanoscale Lg, because of velocity saturation (Fossum and Krishnan, 1993), 2-D effects in the BOX, i.e., electric-field fringing as shown in Fig. 3.1(b) (Yeh and Fossum, 1995), and early technological limits of scaling tSi, the interest subsided, and conventional (i.e., bulk-Si and PD/SOI) CMOS prevailed. With advanced SOI wafer technology, those promoting the nanoscale FD/SOI MOSFET with thin BOX (e.g., Faynot et al., 2010), as opposed to the FinFET, argue that its (planar) process flow is relatively simple, that its SCE control is excellent, and that it enables Vt tuning and power management, or low VDD, via the back-gate, or substrate, design. The measured device characteristics discussed in Sec. 1.1.1 reflect these arguments, while indicating that thick-BOX FD/SOI UTB MOSFETs are still of interest as well. We first overview general device features that are relevant to both thick- and thin-BOX devices, discussing basic analysis of scaling conventional, thick-BOX FD/SOI CMOS and describing, for the thin-BOX design, the unique features, including performance and scalability, stemming from the thin BOX and the back-gate (substrate) design and bias.