The detailed synthesis of a direct access ring filter topology fully controlled with the following targeted specification (center frequency, low transmission zero frequency, and matching level in the passband) is hereby presented. For this topology, the lowest achievable bandwidth is limited by technological constraints. Thereby a solution consisting in adding capacitive loads is proposed. The associated synthesis is also given and discussed. Both syntheses are illustrated with 60 GHz integrated planar filters implemented in the IHP 130 nm BiCMOS technology. Various 3 dB fractional bandwidths from 18 to 8% are targeted, some of them require the implementation of the capacitive loaded solution. The latter allows us to lower the bandwidth limit of the nominal topology as well as to get a high miniaturization, up to 3.4, depending on the capacitance value. Thanks to good measurement results, this implementation highlights the high efficiency, reliability, and versatility of the synthesis without the need of tuning simulations or post-simulations.