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Integration of photonic devices on silicon (Si) substrates is a key method in enabling large scale manufacturing of Si-based photonic–electronic circuits for next generation systems with high performance, small form factor, low power consumption, and low cost. Germanium (Ge) is a promising material due to its pseudo-direct bandgap and its compatibility with Si-CMOS processing. In this article, we present our recent progress on achieving high quality germanium-on-silicon (Ge/Si) materials. Subsequently, the performance of various functional devices such as photodetectors, lasers, waveguides, and sensors that are fabricated on the Ge/Si platform are discussed. Some possible future works such as the incorporation of tin (Sn) into Ge will be proposed. Finally, some applications based on a fully monolithic integrated photonic–electronic chip on an Si platform will be highlighted at the end of this article.
Metamorphic epitaxy offers the possibility of growing devices on wafers composed of different materials that might be larger than the native bulk substrates for a potential cost-reduction of III–V components; this is especially important when native substrates with desired lattice constants are not available. This article reviews the concepts of metamorphic epitaxy of III–V compound semiconductor materials and examines how they have been applied to the development of advanced transistor devices. These metamorphic devices are expected to be a key enabler of future heterogeneous integrated circuits in which Si and III–V devices are monolithically integrated on a wafer scale using complementary metal oxide semiconductor-like process flows.
We report on a direct epitaxial growth approach for the heterogeneous integration of high speed III-V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBTs) structures were successfully grown on patterned Si-on-Lattice-Engineered-Substrate (SOLES) substrates using molecular beam epitaxy. DC and RF performance similar to those grown on lattice-matched InP were achieved in growth windows as small as 15×15μm2. This truly planar approach allows tight device placement with InP-HBTs to Si CMOS transistors separation as small as 2.5 μm, and the use of standard wafer level multilayer interconnects. A high speed, low power dissipation differential amplifier was designed and fabricated, demonstrating the feasibility of using this approach for high performance mixed signal circuits such as ADCs and DACs.
Our direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft of 170GHz at a nominal collector current density of 2mA/μm2. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.
ZnO nanorods are grown by hydrothermal synthesis on a GaN substrate. The nanorods are charcterised by X-ray diffraction, photoluminescence and electron diffraction. A phenomenological model is proposed to predict the areal density and rod length.
In this paper, we present GaAs/Ge heteroepitaxy grown by RIBER32 solid-source Molecular Beam Epitaxy (SSMBE) with initial GaAs nucleation by migration-enhanced epitaxy (MEE) technique. We look at the influence of substrate temperature during the MEE and the influence of Ge surface orientation to the quality of the GaAs layer. Three samples were grown for this study; the first two samples, sample A and B, have surface orientation of (100) 6° offcut towards (111) plane. This surface orientation was chosen as to achieve double-atomic steps surface that is crucial to suppress anti-phase domain (APD) formation. These samples were then subjected to different temperature during the MEE process, 450°C for sample A and 250°C for sample B. The third sample, sample C, has the same MEE substrate temperature as sample A, which is 450°C but with nominal (100) surface orientation. The growth conditions and structure of the layers after the MEE process were kept constant across the three samples.
We examine the structures and the optical quality of the samples by cross-sectional Transmission Electron Microscope (XTEM) and 5K photoluminescence (PL). Analyzing the XTEM images of sample A and B, it is found that the APD still appear in sample A while it is suppressed totally in sample B. It is also observed from sample A XTEM image that two APDs propagating with 45° and 135° angle, as measured from the GaAs/Ge interface, could meet with each other at certain layer thickness leading to self-annihilation. However, some of the self-annihilations took place only after the APDs propagated hundreds of nanometers in the GaAs layer, producing large undulation in the layer. As for sample B, we believe that the APD suppression is mainly due to the much lower nucleation temperature. At such low temperature, As dimers are adsorbed onto the substrate surface more readily with negligible re-evaporation. This ensures complete As coverage on the double-atomic steps Ge surface and minimize As vacancies that may act as defect initiation centers. Furthermore, the low substrate temperature shortens the migration distance of Ga adatoms, minimizing their adsorption into the kinks and step edges, resulting in two-dimensional growth mode instead of step-flow growth mode.
Meanwhile, XTEM image of sample C shows APDs that propagated almost perpendicularly to the GaAs/Ge interface, making it unlikely for the self-annihilation mechanism to take event. It is understood that the direction of propagation of the APD relies on the atomic steps reconstruction of the Ge starting surface. In the case of single atomic-step surface, the APDs propagate almost perpendicularly to the interface. Finally, the 5K PL spectra of the embedded InGaAs single quantum-well in all the samples clearly demonstrate that the best optical quality comes from sample B; which we believe mainly because of the total suppression of APD, leading to much improved layer quality.
We present a framework for obtaining high quality relaxed graded SiGe buffers on Si for III-V integration. By avoiding dislocation nucleation in Si1−xGex layers of x>0.96, we have achieved a relaxed Si0.04Ge0.96 platform on Si(001) offcut 2° that has a threading dislocation density of 7.4×105 cm−2. This 2° offcut orientation was determined to be the minimum necessary for APB-free growth of GaAs. Furthermore, we found that we could compositionally grade the Ge content in the high-Ge portion of the buffer at up to 17 %Ge μm−1 with no penalty to the dislocation density. The reduction in both threading dislocation density and buffer thickness exhibited by our method is an especially significant development for relatively thick minority-carrier devices which use III-V materials such as multi-junction solar cells.
The monolithic integration of high efficiency III-V compound solar cell materials and devices with lower-cost, robust and scaleable Si substrates has been a driving force in photovoltaics (PV) basic research for decades. Recent advances in controlling mismatch-induced defects that result from structural and chemical differences between III-V solar cell materials and Si using a combination of SiGe interlayers and monolayer-scale control of III-V/IV interfaces, have led to a series of fundamental advances at the material and device levels, which establish that the great potential of III-V/Si PV is within reach. These include demonstrations of GaAs epitaxial layers on Si that are anti-phase domain-free with verified dislocation densities at or below 1×106 cm−2 and negligible interface diffusion, minority carrier lifetimes for GaAs on Si in excess of 10 ns, single junction GaAs-based solar cells on Si with open circuit voltages (Voc) in excess of 980 mV, efficiencies beyond 18%, and area-independent PV characteristics up to at least 4 cm2. These advances are attributed in large part to the use of a novel “engineered Si substrate” based on compositionally-graded SiGe buffers such that a high-quality, low defect density, relaxed, “virtual” Ge substrate could be developed that can support lattice-matched III-V epitaxy and thus merge III-V technology based on the GaAs (or Ge) lattice constant with Si wafers. This paper focuses on recent results that extend this work to the first demonstration of high performance III-V dual junction solar cells on SiGe/Si. Open circuit voltages in excess of 2 V at one-sun have been obtained for the conventionally “lattice-matched” In0.49Ga0.51P/GaAs dual junction cells on inactive, engineered SiGe/Si; to our knowledge is the first demonstration of > 2V solar power generation on a Si wafer. Comparisons with identical cells on GaAs substrates reveal that the Voc on engineered Si retains more than 94% of its homoepitaxial value, and that at present both DJ/GaAs and DJ/SiGe/Si cells are similarly limited by current mismatch in these early cells, and not fundamental defect factors associated with the engineered Si substrates.
The use of alternative channel materials such as germanium [1,2] and strained silicon (ε-Si) [3-5] is increasingly being considered as a method for improving the performance of MOSFETs. While ε-Si grown on relaxed Si1-x Gex is drawing closer to widespread commercialization, it is currently believed that almost all of the performance benefit in CMOS implementations will derive from the enhanced mobility of the n -MOSFET . In this paper, we demonstrate that ε-Si p -MOSFETs can be engineered to exhibit mobility enhancements that increase or remain constant as a function of inversion density. We have also designed and fabricated ε-Si / ε-Ge dual-channel p -MOSFETs exhibiting mobility enhancements of 10 times. These p -MOSFETs can be integrated on the same wafers as ε-Si n -MOSFETs, making symmetric-mobility CMOS possible.
The use of alternative channel materials such as germanium [1,2] and strained silicon (ε-Si) [3-5] is increasingly being considered as a method for improving the performance of MOSFETs. While ε-Si grown on relaxed Si1-xGex is drawing closer to widespread commercialization, it is currently believed that almost all of the performance benefit in CMOS implementations will derive from the enhanced mobility of the n-MOSFET . In this paper, we demonstrate that ε-Si p-MOSFETs can be engineered to exhibit mobility enhancements that increase or remain constant as a function of inversion density. We have also designed and fabricated ε-Si / ε-Ge dual-channel p-MOSFETs exhibiting mobility enhancements of 10 times. These p-MOSFETs can be integrated on the same wafers as ε-Si n-MOSFETs, making symmetric-mobility CMOS possible.
Advanced CMOS substrates composed of ultra-thin strained-Si and SiGe-on-insulator were fabricated, combining both the benefits of high-mobility strained-Si and SOI. Our pioneering method employed wafer bonding of SiGe virtual substrates (with strained-Si layers) to oxidized handle wafers. Layer transfer onto insulating handle wafers can be accomplished using grind-etchback or delamination via implantation. Both methods were found to produce a rough transferred layer, but polishing is unacceptable due to non-uniform material removal across the wafer and the lack of precise control over the final layer thickness. To solve these problems, a strained-Si stop layer was incorporated into the bonding structure. After layer transfer, excess SiGe was removed using a selective etch process, stopping on the strained-Si. Within the context of ultra-thin SSOI and SGOI fabrication, this paper describes recent improvements including metastable stop layers, low temperature wafer bonding, and improved selective SiGe removal.
Epitaxial-transparent-substrate light emitting diodes with a primary emission peak at 590nm and a secondary peak at 560nm have been fabricated in the indium aluminum gallium phosphide (InAlGaP) system. The active layer consists of an undoped, compressively strained indium gallium phosphide (InGaP) quantum well on a transparent In0.22(Al0.2Ga0.8)0.78P/ ∇x[1nx(Al0.2Ga0.8)1-xP] /GaP virtual substrate. Theoretical modeling of this structure predicts an accessible wavelength range of approximately 540nm to 590nm (green to amber). Emission with a peak wavelength of 570nm has been observed via cathodoluminescence studies of undoped structures with a quantum well composition of In0.35Ga0.65P. Light emitting diodes have been fabricated utilizing simple top and bottom contacts. The highest LED power of 0.18μW per facet at 20mA was observed for a quantum well composition of In0.32Ga0.68P and a bulk threading dislocation density on the order of 7×106 cm-2. The spectrum of this device was composed of two peaks: a weak peak at the predicted 560nm wavelength and a stronger peak at 590nm. Based upon superspots present in electron diffraction from the quantum well region, we believe that the observed spectrum is the result of emission from ordered and disordered domains in the active region. The same device structure grown with a bulk threading dislocation density on the order of 5×107 cm-2 exhibited an identical spectral shape with a reduced power of 0.08μW per facet at 20mA. For a quantum well composition of In0.37Ga0.63P and an overall threading dislocation density on the order of 5×107 cm-2, a single peak wavelength of 588nm with a power of 0.06μW per facet at 20mA was observed.
We have fabricated strained Ge channel p-type metal oxide semiconductor field-effect transistors (p-MOSFETs) on Si1−xGex (x=0.7 to 0.9) virtual substrates. Capping the channel with a relaxed, epitaxial silicon layer eliminates the poor interface between silicon dioxide (SiO2) and pure Ge. The effects of the Si cap thickness, the strain in the Ge channel, and the thickness of the Ge channel on hole mobility enhancement were investigated. Optimized strained Ge p-MOSFETs show hole mobility enhancements of nearly 8 times that of co-processed bulk Si devices across a wide range of vertical field. These devices demonstrate that the high mobility holes in strained Ge can be utilized in a MOS device despite the need to cap the channel with a highly dislocated Si layer.
Strained Si- and SiGe-based heterostructure metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed SiGe virtual substrates exhibit dramatic electron and hole mobility enhancements over bulk Si, making them promising candidates for next generation complementary MOSFET (CMOS) devices. The most heavily investigated heterostructures consist of single strained Si layers grown upon relaxed SiGe substrates. While this configuration offers significant performance gains for both n- and p-MOSFETs, the enhanced hole mobility remains much lower than the enhanced electron mobility. By contrast, a combination of buried compressively strained Si1−yGey layers and tensile strained Si surface layers grown on relaxed Si1−xGex (x < y), hereafter referred to as dual channel heterostructures, offers nearly symmetric electron and hole mobilities without compromising n-MOSFET device performance. To investigate these heterostructures, we study the effects of alloy scattering on channel mobility in long channel MOSFETs. By using the combination of a buried Si0.2Ge0.8 channel and a strained Si surface channel grown on a relaxed Si0.5Ge0.5 virtual substrate, we have achieved nearly symmetric electron and hole mobility in the same heterostructure. By employing different virtual substrate compositions, we can decouple the effects of strain and alloy scattering in both tensile strained surface channels and compressively strained buried channels. We show that significant hole mobility enhancements can be achieved in dual channel heterostructures, even for buried channel compositions where alloy scattering is expected to be most severe. Furthermore, we show that alloy scattering in tensile strained SiGe surface channels impacts electrons much more severely than holes. Taken together, these results demonstrate that dual channel heterostructures can offer symmetric carrier mobilities and provide excellent performance gains for CMOS applications.
We have fabricated high quality SGOI substrates and demonstrated high mobility enhancement in strained-Si MOSFET's fabricated on the relaxed SGOI substrates with a Ge content of 25%. The substrates were fabricated by wafer bonding. The initial relaxed Si1−xGex layers were grown on Si donor substrates by a graded epitaxial growth technology using ultrahigh vacuum chemical vapor deposition (UHVCVD). The SiGe wafers were then bonded to oxidized silicon handle wafers. Two different approaches have been developed to fabricate SGOI substrates: an etch-back process utilizing a 20% Ge layer as a natural etch stop, and a hydrogen-induced wafer delamination process using H+ implantion. The resultant SiGe film quality was compared among the different approaches. Large-area strained-Si MOSFET's were then fabricated on the SGOI substrates. Epitaxial regrowth was used to produce the upper portion of the relaxed SiGe and the surface strained Si layer. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFET's. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si1−xGex layer.
AlxGa(1−x)As/GaAs quantum well lasers have been demonstrated via organometallic chemical vapor deposition (OMCVD) on relaxed graded GexSi(1−x) virtual substrates on Si. Despite unoptimized laser structures with high series resistance and large threshold current densities, surface threading dislocation densities as low as 2×106 cm−2 enabled cw room-temperature lasing at a wavelength of 858nm. The laser structures are oxide-stripe gain-guided devices with differential quantum efficiencies of 0.16 and threshold current densities of 1550A/cm2. Identical devices grown on commercial GaAs substrates showed differential quantum efficiencies of 0.14 and threshold current densities of 1700A/cm2. This comparative data agrees with our previous measurements of near-bulk minority carrier lifetimes in GaAs grown on Ge/GeSi/Si substrates. A number of GaAs/Ge/Si integration issues including thermal expansion mismatch and Ge autodoping behavior in GaAs were overcome.
Germanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz frequencies in the 1–1.6 μm wavelength regime. The compatibility of SiGe alloys with Si substrates makes Ge a natural choice for photodetectors in Si-based optoelectronics applications. The large lattice mismatch (≈4%) between Si and Ge, however, leads to the formation of a high density of misfit and associated threading dislocations when uniform Ge layers are grown on Si substrates. High quality Ge layers were grown on relaxed graded SiGe/Si layers by ultra-high vacuum chemical vapor deposition (UHVCVD). Typically, as the Ge concentration in the graded layers increases, strain fields from underlying misfit dislocations result in increased surface roughness and the formation of dislocation pile-ups. The generation of pile-ups increases the threading dislocation density in the relaxed layers. In this study the pileup formation was minimized by growing on miscut (001) substrates employing a chemical mechanical polishing (CMP) step within the epitaxial structure. Other problems such as the thermal mismatch between Si and Ge, results in unwanted residual tensile stresses and surface microcracks when the substrates are cooled from the growth temperature. Compressive strain has been incorporated into the graded layers to overcome the thermal mismatch problem, resulting in crack-free relaxed cubic Ge on Si at room temperature. The overall result of the CMP step and the growth modifications have eliminated dislocation pile-ups, decreased gas-phase nucleation of particles, and eliminated the increase in threading dislocation density that occurs when grading to Ge concentrations greater than 70% Ge. The threading dislocation density in the Ge layers determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range of 2 × 106/cm2. Ge p-n diodes were fabricated to assess the electronic quality and prove the feasibility of high quality photodetectors on Si substrates.