To eliminate the interface reaction problems between ferroelectric and semiconductor in MFS (metal-ferroelectric-semiconductor) as well as ferroelectric and insulator in MFIS (metal-ferroelectric-insulator-semiconductor) structures, a gate layer sandwich of the MFMIS (metal-ferroelectric-metal-insulator-semiconductor) is proposed. This structure consists of Pt-SBT-Pt-ZrO2-SiO2-Si stacks. In the MFMIS structure the MIS capacitor is separated from the ferroelectric MFM capacitor through a metal as a floating gate. Therefore, the MIS capacitor with SiO2 and ZrO2 as an insulator with excellent interface properties can be used and MFM acts as an ideal ferroelectric capacitor. As MFMIS is a series combination of MFM and MIS capacitors, it behaves as a voltage divider. The gate voltage is divided according to the capacitance ratio of the MIS and MFM structures. Since the fabricated devices have access to the floating gate, characteristics of the MFM and MIS capacitors can be determined independently to compare the characteristics of the MFMIS structure as a single capacitor. The ferroelectric can be programmed in one direction and the field effect due to that can be analyzed. The MFMIS structures showed significant memory window due to the polarization of ferroelectric thin films but the retention time was short. The short retention time was due to the depolarization field being larger than coercive field of the ferroelectric thin film.