The current status of SiC bulk growth is reviewed, while specific
attention is given to the effect of defects in SiC substrates and
epitaxial layers on device performance and yield. The progress in SiC
wafer quality is reflected in the achievement of micropipe densities
as low as 0.92 cm−2 for a 3-inch n-type 4H-SiC wafer, which
provides the basis for a high yielding fabrication process
of large area SiC power devices. Using a Murphy Probe Yield Analysis for the
breakdown characteristics of 10 kV PiN diodes we have extracted
an “effective” defect density for 4H-SiC material to be as low as
30 cm−2, providing valuable information to further isolate and
address the specific material defects critical for device performance.
We address the problematic degradation of the forward characteristics
-drift) of bipolar SiC PiN diodes [CITE].
The underlying mechanism due to stacking fault formation in the epitaxial
layers and possible effects of device processing are investigated.
An improved device design is demonstrated, which effectively stabilizes
-drift. We show the progression in the development of
semi-insulating SiC grown by the sublimation technique from extrinsically
doped material to high purity semi-insulating (HPSI) 4H-SiC bulk crystals of
up to 100 mm diameter without resorting to the intentional introduction
of elemental deep level dopants, such as vanadium. Uniform resistivities
in 3-inch HPSI wafers greater than 3 × 1011 Ω-cm
have been achieved. Secondary ion mass spectrometry, deep level transient
spectroscopy and electron paramagnetic resonance data suggest that the
semi-insulating behavior in HPSI material originates from deep levels
associated with intrinsic point defects. MESFETs produced on HPSI wafers
are free of backgating effects and have resulted in the best combination of
power density and efficiency reported to date for SiC MESFETs of
5.2 W/mm and 63% power added efficiency (PAE) at 3.5 GHz.