Conventional and self-aligned processes were developed for 250 °C inverse-staggered bottom gate a-Si:H thin film transistors (TFT's). Tri-layers of silicon nitride, amorphous silicon, and silicon nitride were continuously deposited in a plasma enhanced chemical vapor deposition system (PECVD). A self-alignment technique including back-side exposure and top nitride over etch was developed, which eliminates a masking step and the critical alignment of via opening used in typical TFT processing. Full self-aligned TFT's formed by selective n+ deposition were also fabricated successfully. Transistors show linear mobility ranging from 0.7 to 1.0 cm2/Vs, and current ON/OFF ratios greater than 106 were achieved for all TFT's.