We incorporate an additional semiconductor heterostructure beneath the transistor channel region to increase the strain-transfer efficiency of lattice-mismatched source/drain (S/D) stressors, resulting in higher strain levels in the channel region. The additional structure is lattice-mismatched with respect to the overlying Si-channel and/or with respect to the S/D stressors. For an n-FET with Si:C S/D, a SiGe region integrated beneath the Si-channel enhances the magnitude of the tensile strain in the channel region. For a p-FET with SiGe S/D, a Si:C region beneath the Si-channel enhances the strain effect in the channel region. This additional structure beneath the transistor channel is called a strain-transfer structure (STS). Extensive numerical simulations were performed using the finite element method to explain how the new strain-transfer structure works. Profiles of the various strain components in the transistor channel were obtained. Dependence of the strain effect on geometrical features of the new transistor structure will also be reported.