We have investigated the effect on a silicon surface of both wet chemical and cluster-tool UV/ozone cleaning, prior to UHV processing to fabricate MOS test structures. The physical and chemical condition of the Si surface has been examined by Scanning Tunnelling and Atomic Force Microscopy (STM, AFM) and Medium Energy Ion Scattering (MEIS). After MOS fabrication some of the structures were examined by Cross-sectional Transmission Electron Microscopy (TEM). The electrical performance of the MOS test sets were characterized by breakdown voltage measurements.
We have found correlations between the electrical performance of the MOS devices, the structure of the Si surface prior to oxidation, and the details of the UHV fabrication technique. In particular any MOS device fabricated on a Si surface thermally cleaned in UHV prior to oxidation has a poor breakdown strength. We have found that this is the result of the formation of silicon carbide on the Si surface at high temperature and the subsequent local disruption of the oxidation step of MOS fabrication by the SiC. A UHV cleaning procedure has been developed to avoid this C contamination problem.