Due to a rapid shrinkage in memory devices, backned of the line process experiences great difficulties, especially Al metallization. Furthermore, there is a continuous demands in low line resistance in order to promote device performances. In this article, Al damascene process is proposed as compared to Al patterning process, which suffers from inherent pattering issue at a fine pitch under 70nm. The most difficulties in the development of Al damascene process were to form a stable and void free Al in fine trench and to obtain scratch and corrosions free Al surface. In this study, 50nm beyond fill was successfully achieved by “bottom up growth” of CVD Al. For the process, CVD Al by using Methylpyrroridine Alane (MPA) precursor was deposited on a stacked film of CVD TiN and PVD TiN as a wetting layer, which was followed by PVD Al and reflow, then the Al surface was polished with colloidal silica based slurry.
In addition, electrical property of Al scheme and W scheme was compared with damascene pattern, along with which we demonstrated that around 36% decrease in parasitic capacitance is achievable by decrease of metal line height from 3500A to 1000A on simulation test implying that device performance could be enhanced.