Conductive atomic force microscopy (C–AFM) in ultra high vacuum (UHV) has been used to characterize charge trapping in ultrathin as–deposited oxide films of 2–4 nm (HfO2)x(SiO2)1-x/SiO2 multilayer gate stacks. Pre– and post–stress/breakdown (BD) dielectric degradation is analyzed on a nanoscale. A systematic observation probes stress induced trap generation facilitating physical stack BD. Degradation is considered in terms of the pronounced localized leakage contribution through the high–κ and interlayer SiOx. Simultaneous nanoscale current–voltage (I-V) characteristics and C–AFM imaging illlutrates charge trapping/decay from the native or stress induced traps with intrinsic charge lateral propagation. A post–stress/BD constant voltage imaging shows effects of stress bias polarity on the BD induced topography and trap assisted nano–current variations. Physical attributes of deformed artifacts relate strongly to the polarity of electron injection (gate or substrate) so discriminating the trap generation in high–κ and interlayer SiOx revealing non–homogeneous (dynamic) nature of leakage.