To send content items to your account,
please confirm that you agree to abide by our usage policies.
If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account.
Find out more about sending content to .
To send content items to your Kindle, first ensure firstname.lastname@example.org
is added to your Approved Personal Document E-mail List under your Personal Document Settings
on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part
of your Kindle email address below.
Find out more about sending to your Kindle.
Note you can select to send to either the @free.kindle.com or @kindle.com variations.
‘@free.kindle.com’ emails are free but can only be sent to your device when it is connected to wi-fi.
‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.
The Parkes radio telescope has been used to search a list of small, dense southern dark clouds and Bok globules for ammonia emission at 23.7 GHz. The ammonia observations, together with IRAS data and the cloud’s visual appearance, have been used to determine a short list of dark clouds for observation with the infrared imaging system (IRIS) on the Anglo-Australian Telescope, in an attempt to determine the dust density distribution within the clouds. Near-infrared images of a number of the short listed clouds have been obtained with IRIS at J, H and K’. Preliminary results are reported for this ammonia survey, together with IRIS images of the strong ammonia source DC 297.7–2.8. Coincident with the dense ammonia core of this object is an IRAS ‘core’ source, IRAS 11590–6452 and an extremely interesting near-infrared source, which lies on the edge of the error ellipse of the IRAS source.
Ammonia formation in autothermal reforming process was studied in Nuvera's Modular Pressurized Flow Reactor facility. Experiments were conducted to study and compare different catalysts for their ammonia formation characteristics. Different hydrocarbon fuels were reformed and effects of fuel structure and operating conditions on ammonia formation were investigated. Reformate generated was analyzed for ammonia contamination by using FTIR spectroscopy.
Epitaxial, ferroelectric Ba2Bi4Ti5O18 films grown on LaNiO3/CeO2/ZrO2:Y2O3 epitaxial layers on Si(100) are investigated by cross-section high-resolution transmission electron microscopy (HRTEM). The films are perfectly oriented and consist of well-developed grains of rectangular shape. The grain boundaries are strained and contain many defects, especially a new type of defect, which can be described as a staircase formed by repeated lattice shifts of Δ ∼ c/12 ∼ 4.2 Å in the  direction. This repeated shift results in seemingly bent ribbons of stacked Bi2O2 planes, involving, however, individual Bi2O2 planes which remain strongly parallel to the (001) plane. These defects contain an excess of bismuth. Other defects found in the grain interior include mistakes in the stacking sequence originating from the presence of single, well-oriented, non-stoichionietric layers intergrown with the stoichiometric Ba2Bi4Ti5O18 film matrix.
Fabrication and characteristics of high voltage, normally-on JFETs in 4H-SiC are presented. The devices were built on 5x1015 cm-3 doped, 12 μm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 10 m Ω-cm2 and a blocking voltage of 1.8 kV were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by a factor of 5 and a decrease in transconductance were observed at 300oC, when compared to the value at room temperature. This is due to a decrease in bulk electron mobility at elevated temperature. A slight negative shift in pinch-off voltage was also observed at 300oC. The devices demonstrated robust DC characteristics for temperatures up to 300oC, and stable high temperature inverter operation in a power DC-DC converter application, using these devices, is reported in this paper.
The reduction in the current gain of SiC BJTs has been observed after operating the devices for as little as 15 minutes. It is accompanied by an increase in the on-resistance of the BJT. The origin of the current gain degradation in the BJTs is investigated. Two possible mechanisms, which may be simultaneously present in the device, are thought to be responsible: (a) increase in the surface recombination particularly in the region between the emitter and the base implant, and (b) bulk recombination in the base due to the generation and growth of stacking faults. Initial observation reveals the presence of stacking fault in the base-emitter region when the device is forward-biased. At the same time, minimizing the effect of recombination from the surface using improved passivation helped in the suppression of the current gain degradation in SiC BJTs.
Improved AlNi-based ohmic contacts to p-type 4H-SiC have been achieved using low energy ion (Al+) implantation, the addition of a thin Ti layer, and a novel two-step implant activation anneal process. Resistivities sometimes as low as 5×10−5 Ω-cm2 were reached by doping the surface region of lightly p-doped 4H-SiC epilayers via low energy Al+ implantation. Acceptor activation was achieved by annealing the samples with a 1400+1700°C two-step sequence in an Ar atmosphere, which also yielded improved surface morphology when implanted samples were capped with photo resist during the anneals. In this study, Ti/AlNi/W contacts on implanted layers were compared to Ti/AlNi/Au contacts. Even though the resistivities are higher than those of the Ti/AlNi/W system, the reduced anneal temperature, 650°C for Ti/AlNi/Au compared to 950°C for Ti/AlNi/W implies that Ti/AlNi/Au is a promising stacking configuration. Furthermore, the effects of a longer 30 minute anneal time at 600 − 700°C, in atmospheric pressure Ar ambients was observed. Namely, the 2 minute annealing cycle used for the Ti/AlNi/W study resulted in higher anneal temperatures before ohmic characteristics were seen. This same anneal time was not sufficient for the Ti/AlNi/Au samples, whereas increasing the cycle time to 30 minutes resulted in ohmic behavior at a much lower temperature. Increasing the anneal time however, had little or no impact on reducing the required anneal temperature of the Ti/AlNi/W.
This paper reports our effort to develop amorphous hydrogenated silicon carbide (a-SiC:H ) films specifically designed for MEMS applications using a semiconductor-grade organosilane known as trimethylsilane (3MS) as the precursor. In our work, the a-SiC:H films were deposited in a commercial PECVD system at a fixed temperature of 350˚C using 3MS diluted in helium (He). Films with thicknesses from ~ 100 nm to ~ 2μm, a typical range for MEMS applications, were deposited. Deposition parameters such RF power, deposition pressure, and 3MS-to-He ratio were explored to obtain films with low residual compressive stresses. Low temperature, post-deposition annealing at 450˚C was used to convert the as-deposited compressive residual stresses to moderate tensile stresses, which are desired for micromachined bridges, membranes and other anchored structures. Compositional analysis indicated that films with a Si-to-C ratio of 1 could be deposited under certain conditions. Mechanical properties such as Young's modulus and fracture strength were derived from the load-deflection behavior of micromachined freestanding membranes. Nanoindentation was used to verify the Young's modulus and determine the hardness. As expected, the films exhibit insulating properties with a relative dielectric constant at 3.90 for as-deposited films and 2.69 after annealing at 1100˚C, as determined from C-V measurements. Chemical inertness was tested in aqueous, corrosive solutions such as KOH and HNA. Prototype structures were fabricated using both surface micromachining and bulk micromachining techniques to demonstrate the potential of the a-SiC:H films for MEMS applications.
Fabrication and characteristics of high voltage, high speed DMOSFETs in 4H-SiC are presented. The devices were built on 1.2×1016 cm-3 doped, 6 mm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 8.7 mW-cm2 and a blocking voltage of 950 V were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by 35% observed at 300oC, when compared to the value at room temperature. This is due to a negative shift in MOS threshold voltage, which decreases the MOS channel resistance at elevated temperatures. This effect cancels out the increase in drift layer resistance due to a decrease in bulk electron mobility at elevated temperature, resulting in a temperature stable on-resistance. The device operation at temperatures up to 300 oC and high speed switching results are also reported in this paper.
The commercialization of 4H-SiC MOSFETs will greatly depend on the reliability of gate oxide. Long-term gate oxide reliability and device stability of 1200 V 4H-SiC MOSFETs are being studied, both under the on- and off-states. Device reliability is studied by stressing the device under three conditions: (a) Gate stress - a constant gate voltage of +15 V is applied to the gate at a temperature of 175°C. The forward I-V characteristics and threshold voltage are monitored for device stability, (b) Forward current stress – devices are stressed under a constant drain current of Id = 4 A and Vg = 20 V. The devices were allowed to self-heat to a temperature of Tsink = 125°C and the I-V curves are monitored with time, and (c) High temperature reverse bias testing at 1200 V and 175°C to study the reliability of the devices in the off-state. Our very first measurements on (a) and (b) show very little variation between the pre-stress and post-stress I-V characteristics and threshold voltage up to 1000 hrs of operation at 175°C indicating excellent stability of the MOSFETs in the on-state. In addition, high temperature reverse bias stress test looks very promising with the devices showing very little variation in the reverse leakage current with time.
In this paper we report the first 4H-SiC CMOS inverter, which was designed to be integrated in the process flow of a 4H-SiC power DMOSFET. The channels of both of the n channel and p-channel MOSFETs of the inverter were 50 um wide by 3 um long. NMOSFET threshold voltage (VTH) ranged from 4.4 V at 25°C to 2.2 V at 250°C and PMOSFET VTH ranged from -4.75 V at 25°C to just under -4 V at 300°C. The transfer threshold voltage (Vm) of the 4H-SiC CMOS inverter was in a very tight range of 2.8 V to 2.9 V over the entire temperature range of 25°C to 300°C when using a drive voltage (VDD) of 10 V.
We have observed a gate-bias stress induced instability in both the threshold voltage of SiC MOSFETs and the flatband voltage of SiC MOS capacitors. The magnitude of this bias stress-induced instability generally increases linearly with log time, with no saturation of the effect observed, even out to 100,000 seconds. The magnitude also increases with increasing gate field. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with electron tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The effect is repeatable.
We present an extended version of our earlier shear-transformation-zone theory of amorphous plasticity that takes into account thermally assisted molecular rearrangements. As in the previous low-temperature theory a transition is predicted between jammed and flowing states at a well defined yield stress. In the new theory the jammed state below the yield stress exhibits thermally assisted creep. The theory accounts for the experimentally observed strain-rate dependence of the viscosity of a bulk metallic glass. In particular it models the onset of superplastic behavior at high strain rates as the system approaches the yield stress. The theory also captures many of the details of the transient stress-strrain response of the metallic glass at temperatures near the glass transition.
Three dimensional models of single chip SiC power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, and heat transfer coefficients on temperature and thermal stress contours. Silicon nitride, aluminum-nitride, alumina were compared as substrates with or without an additional layer of CVD diamond on either top or bottom of the surfaces. Simulated heat fluxes of 100 to 300 watts/cm2 resulted in device junction temperatures in the range of 377 to 535 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 3350 watts/m2 K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 535 K. Both the maximum and minimum chip temperature decreased with increasing heat transfer coefficient from 50 to 5000 watts/m2 K. In the applied heat flux range, the minimum and maximum Von Mises stress of a simulated single SiC device sub-module was between 946 MPa to 1.31GPa. If consistent with simulation results, CVD diamond integrated substrates should be superior to those comprised of only AlN, Al2O3, and Si3N4. Experimental validation of ANSYS results and more extensive multiple-chip power module simulations will also be explored.
A systematic study is presented of the heteroepitaxial growth of B12As2 on m-plane 15R-SiC. In contrast to previous studies of B12As2 on other substrates, including (100) Si, (110) Si, (111) Si and (0001) 6H-SiC, single crystalline and untwinned B12As2 was achieved on m-plane 15R-SiC. Observations of IBA on m-plane (1100)15R-SiC by synchrotron white beam x-ray topography (SWBXT) and high resolution transmission electron microscopy (HRTEM) confirm the good quality of the films on the 15R-SiC substrates. The growth mechanism of IBA on m-plane 15R-SiC is discussed. This work demonstrates that m-plane 15R-SiC is potentially a good substrate choice to grow high quality B12As2 epilayers.