Practical use of amorphous silicon stacked-junction color detectors in large-area arrays requires periodic readout of the photo-charge stored in the capacitance of the device by a transient technique of sensing. In any stacked-junction devices, color information is obtained by the “self-biasing” process: during an integration time, the three junctions independently lose charge; during the readout pulse, the capacitances of the three junctions in electrical series are re-charged. Equilibrium is reached after a few cycles, when the charge integrated in a cycle by each junction is the same, and equals the readout charge. The amount of charge is determined by the reverse biased junction and accounts for the light intensity.
Dimensioning the amorphous silicon Thin Film Transistor (TFT) used as a pixel switch for the detector is a critical part of the project of a color imager. The actual design determines the self-bias process duration and the readout accuracy. The typical large thickness difference between the detector junctions makes the constraints for the switching process extremely demanding: since a greater capacitance is expected in the thinner top junction detecting blue radiation, the on-resistance must be reduced. Since the front junction does not ensure full rejection of green and red light, a calculation must be performed to extract the information on blue radiation. This requires further precision in the readout process.
In this work we present a simulation study of the self-biasing process. Both a-Si:H TFT and the a-Si:H p-i-n-i-p two-color detectors are simulated by a finite-elements two-dimensional simulator ensuring a correct modeling of both the devices. Simulations allow to study in detail the timing and the accuracy of the self-biasing process. Including electrostatic capacitance and trapped charge, a set of design rules for the TFT is achieved in terms of on-state design. Similar considerations can be extended to the case of ATCD three-color detectors.