Since the end of the last millenium, the microelectronics industry has been
facing new issues as far as CMOS devices scaling is concerned. Linear
scaling will be possible in the future if new materials are introduced in
CMOS device structures or if new device architectures are implemented.
Innovations in the electronics history have been possible because of the
strong association between devices and materials research. The demand for
low voltage, low power and high performance are the great challenges for the
engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in
the range of 5 nm channel length have been demonstrated. The alternative
architectures allowing to increase devices drivability and reduce power
consumption are reviewed. The issues in the field of gate stack, channel,
substrate, as well as source and drain engineering are addressed. HiK gate
dielectric and metal gate are among the most strategic options to consider
for power consumption and low supply voltage management. By introducing new
materials (Ge, diamond/graphite carbon, HiK, ...), Si based CMOS will be
scaled beyond the ITRS as the future System-on-Chip Platform integrating
also new disruptive devices. For example, the association of C-diamond with
HiK, as a combination for new functionalized Buried Insulators, will bring
new ways of improving short channel effects and suppress self-heating.
Because of the low parasitics required to obtain high performance circuits,
alternative devices will hardly compete against logic CMOS.