A technical trend for a-Si TFTs is their application to large-size, high-pixel density AMLCDs such as XGA, EWS, and HDTV. In order to realize these LCDs, the TFT device characteristics must be improved. Future technologies, which will be necessary to fabricate TFTs with improved characteristics are as follows,

(1) Fully self-aligned TFT technology: A SA-TFT structure reduces the feedthrough voltage caused by parasitic capacitance due to gate/source overlap. This results in an improved picture quality and a higher aperture ratio. Fabrication of such a structure would require ion doping technology.

(2) Ion doping technology: This non-mass-separated implantation technique has large area doping capability and much higher doping speed compared to conventional ion implantation technique. The major problems with the ion doping technique is the implantation of unwanted species which deteriorate the quality of source/drain and channel regions of TFTs.

The key requirements for photovoltaic modules to be accepted for large-scale terrestrial applications are (i) low material cost, (ii) high efficiency with good stability, (iii) low manufacturing cost with good yield and (iv) environmental safety. Thin films of amorphous silicon alloy are inexpensive; the products are also environmentally benign. The challenge has been to improve the stable efficiency of these modules and transfer the R&D results into production. Using a multijunction, multi-bandgap approach to capture the solar spectrum more efficiently, we have developed one-square-foot modules with initial efficiency of 11.8% After 1000 h of one-sun light soaking, a stable efficiency of 10.2% was obtained. Both the efficiency values were confirmed by National Renewable Energy Laboratory. The technology has been transferred to production using an automated roll-to-roll process in which different layers of the cell structure are deposited in a continuous manner onto stainless steel rolls, 14′ wide and half a mile long. The rolls are next processed into modules of different sizes. This inexpensive manufacturing process produces high efficiency modules with subcell yields greater than 99% The key features of the technology transfer and future scope for improvement are discussed.

Multi-layer devices based on thin films in Large Area Electronics have different intrinsic and extrinsic properties that must be optimised to produce the correct physical shape of the device, in addition to having acceptable electrical characteristics. For instance it is quite easyto produce individual layers optimised for electrical performance that will physically “pull off” underlying films, or result in poor step coverage. The factors that must be considered include mechanical stress, etching rates and profiles, thickness and stoichiometry uniformity, and thermal budgets, as well as electrical characteristics. This paper gives an example of silicon nitride optimisation for use in a-Si:H TFT projection displays. Three different silicon nitride layers were included to give a storage capacitor, together with controlled etch profiles for step coverage. The layers were optimised with respect to several different parameters in the minimum number of depositions by the use of experimental design techniques.

We fabricated the high performance a-Si:H TFT using the N2 plasma treated APCVD SiO2 as a gate insulator. The effects of N2 plasma treatment on the APCVD SiO2 were investigated by XPS and SIMS measurements. And the formation of the oxynitride interface layer between a-Si:H and APCVD SiO2 was found in the a-Si:H TFT. From our experimental results, It may be concluded that most nitrogen atoms, which were incorporated by the exposure of SiO2 layer to N2 plasma, exist, not bonded to other atoms, near the surface of the SiO2 layer and during the sequential deposition of a-Si:H on the N2 plasma treated APCVD SiO2 layer Si-N bonds are formed, resulting in the oxynitride layer in the interface region. This explains the high performance a-Si:H TFT with the N2 plasma treated APCVD SiO2 gate insulator.

We have studied the effect of ion doping on the electrical properties for atmospheric pressute chemical vapor deposition (APCVD) amorphous silicon (a-Si) films. The room temperature conductivities after ion doping at optimurr doping tenperatures for n− and p-type a-Si films were found to be > 10−2 and >10−4 S/cm, respectively. The unintentional hydrogen incorporation into a-Si during ion doping enhances the quality of ion doped APCVD a-Si as compared to that of plasma enhanced CVD (PECVD) a-Si:H. We obtained the field effect mobility of > 1 cm2/Vs for APCVD a-Si TFT using ion doped n+-layer.

The combination of a-Si low leakage pixel TFTs with poly-Si TFTs in peripheral circuits provides an excellent method for reducing the number of external connections to large-area imaging arrays and displays. To integrate the fabrication of the peripheral poly-Si TFTs with the a-Si pixel TFTs, we have developed a threestep laser process which enables selective crystallization of PECVD a-Si:H. X-ray diffraction and transmission electron microscopy show that the polycrystalline grains formed with this three-step process are similar to those crystallized by a conventional one step laser crystallization of unhydrogenated amorphous silicon. The grain size increases with increasing laser energy density up to a peak value of a few microns. The grain size decreases with further increases in laser energy density. The transistor field effect mobility is correlated with the grain size, increasing gradually with laser energy density until reaching its maximum value. Thereafter, the transistors suffer from leakage through the gate insulators. A dual dielectric gate insulator has been developed for these bottom-gate thin film transistors to provide the correct threshold voltages for both a-Si and poly-Si TFTs.

We have previously demonstrated selective area deposition of n+ microcrystalline silicon at 250°C using time modulated silane flow into a hydrogen plasma, and applied the technique to form high performance top-gate amorphous silicon TFT's with two mask sets. In this paper, we discuss issues related to process scale-up, including the effect of deposition rate on selectivity loss and non-uniformity. Uniformity can be achieved with higher growth rates by expanding the window for selectivity, and using conditions well within the process limits. We show that lower pressure and higher rf power can enlarge the window by enhancing the hydrogen-mediated silicon etching.

The drive-current of low-temperature (∼300°C) deposited TFTs has been increased by replacing the a-Si:H channel, and source and drain materials with μc-Si. Lightly B2H6 doped, near-intrinsic μc-Si has been used as the channel layer of the TFTs, and n+ μc-Si was used for the source and drain contacts. The compensation of intrinsic defects in the undoped μc-Si by boron doping increases the dark conductivity activation energy from ∼0.35 eV to 0.8 eV. TFI's were fabricated in a bottom gate structure, and required an H2 plasma treatment to produce devices with effective channel mobilities of ∼6.8 cm2/V-s and threshold voltages of ∼3.7 V in the saturation region.

A novel technique has been proposed for selective and in -situ excimer-laser crystallization and doping to thin poly-Si films. Dopant atoms are supplied, during the Si laser crystallization process, to the Si film on glass from the doped SOG (spin-on-glass) film coated on the top. Conductivity of the processed film was increased to more than 10S/cm from about 10−8S/cm of the starting film. This technique has been applied to the bottom gate amorphous-Si TFTs with self-aligned poly-Si source and drain. The electron field-effect mobility was 1.0cm2/Vs and the on/off current ratio was more than 106. No parasitic effects were observed, and the hole conduction was effectively. This in-situ crystallization and doping technique can also be applied to the top gate a-Si TFT process.

Inverted-staggered hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs) were deposited in a glow discharge with an excitation frequency of 60 MHz. At 13.56 MHz it has been reported that the field-effect mobility of this type of TFT decreases with increasing deposition rate of the a-Si:H layer, due to an increase in the defect density in the channel. A successful way of increasing the deposition rate without deteriorating the material properties has turned out to be utilizing a higher excitation frequency than the conventional 13.56 MHz.

The deposition rate of the 60-MHz-deposited transistor channel was changed from 350 to 1300 Å/min by diluting the process gas silane with hydrogen and by changing the rf power. The dependence of the a-Si:H material properties on deposition parameters is described. The deposition rate dependence of the mobility in the 60-MHz deposited thin films and devices is presented and discussed in terms of hydrogen dilution in the plasma and the hydrogen content of the a-Si:H films.

The amorphous silicon thin transistor (a-Si TIFT) has successfully industrialized the active matrix liquid crystal displays (AMLCDs), which would get a vast market on the basis of their wide potential use for displays. Whereas, the polysilicon TFT (p-Si TFT) also has been intensely investigated and intended to realize smarter AMLCDs, with monolithic peripheral circuits.

In this paper, we will discuss the applicable range of low temperature p-Si TFTs compared with high temperature p-Si TFTs. After reviewing the materials which comprise low temperature p-Si TFTs, we will introduce our self aligned aluminum gate process which could allow fast addressing even in enlarged AMLCDs in the future.

An extensive study is reported here on plasma enhanced crystallization of a-Si:H films on glass. Both electron cyclotron resonance (ECR) helium plasma exposures and ECR oxygen plasma exposures were investigated to obtain enhanced crystallization of a-Si:H films. We have found that the ECR helium plasma exposure can render more crystallization enhancement than the ECR oxygen plasma exposure. This is because ECR helium plasma exposures can produce more dangling Si bonds, voids, and “interstitial” Si atoms in a-Si:H films than ECR oxygen plasma exposures. These dangling Si bonds, voids, and “interstitial” Si atoms are believed to be the cause of the observed reduced incubation time as well as enhanced grain growth of the plasma exposed a-Si:H films in subsequent crystallization processes. This model is supported by the effects of plasma exposure time on the enhanced crystallization process of a-Si:H films.

We have fabricated polysilicon (poly-Si) thin film transistors (TFTs) using a standard 4-mask sequence, with self-aligned ion implantation for source and drain doping. The active layer was obtained by solid phase crystallisation of high purity Si2H6-deposited amorphous Si, whereas the gate oxide was synthesised by a novel plasma deposition technique, namely distributed electron cyclotron resonance plasma enhanced chemical vapour deposition (DECR PECVD). We have obtained high carrier mobilities (70 cm2V−1s−1 for electrons and 40 cm2V−1s−1 for holes) with an excellent uniformity and without the need for a post-hydrogenation treatment. Moreover, we show that the TFT characteristics are practically insensitive to hot carrier effects.

The crystallization of LPCVD a-Si by Rapid Thermal Anneal was investigated. RTA polysilicon films can find application in the fabrication of TFTs for AMLCDs, due to the lower thermal budget associated with fast crystallization at high temperatures. It was found that the grain size of the crystallized films decreases with the temperature, in the range of 700°C to 1100°C, while for higher temperatures the opposite trend is observed. The latter observation was attributed to the high thermal vibration of subcritical clusters, that was assumed responsible for the decline in the nuclei population at high annealing temperatures, combined with the faster crystalline growth rate at high temperatures. RTA silicon films were found to have lower intra-grain defect density, that may result in the improvement of the electrical characteristics of the polysilicon films.

We have studied the effect of O2 plasma exposure on the performance of polycrystalline silicon (poly-Si) thin film transistor (TFTs). The field effect mobility is increased and the drain currents at negative gate voltages are reduced by O2 plasma exposure on the surface of the TFT. These improvements in the performance of the poly-Si TFTs are larger in offset structure compared to overlap one. We obtained the on/off current ratio of ∼ 108 after O2 plasma exposure for the poly-Si TFTs with 3 or 4 μm offset length.

XPS measurement showed that undesirable SiNH component was reduced drastically from the low-temperature deposited SiN surface by intense ArF excimer-laser irradiation. Although the improved layer was as thin as 15nm, it was very effective to stop diffusion of N atoms from the bottom SiN layer to the top Si layer during the excimer-laser recrystallization step. N-diffused Si layer at the Si/SiN interface was less than the XPS resolution limit for the pre-annealed SiN structure, but about 5nm thick. As a result, the field-effect mobility of the poly-Si/SiN TFT was increased drastically by laser-irradiation to SiN film. Annealing characteristics are also presented for the various SiN film thicknesses and for both the ArF and KrF excimer-laser lights.

We investigated the solid phase crystallization (SPC) behavior of 1000 Å amorphous Si (a- Si) films deposited by plasma enhanced chemical vapor deposition (PECVD) at various temperatures and were able to enhance the grain size of the crystallized polysilicon films using double layers of a-Si filns. The deposition temperature of monolayer a-Si films varied from 200 to 400 °C and the films were recrystallized at 600 °C in nitrogen. As the deposition temperature increased, the incubation time was decreased and both the nucleation rate and growth rate were increased. Especially, the nucleation rate strongly depended on the deposition temperature.

Since the Si-SiO2 interface provides a large number of nucleation sites, it is desirable to suppress nucleation at the interface. As an idea we employed a structure with double layer a-Si films. The bottom a-Si layer deposited at lower temperature could suppress the nucleation at the Si-SiO2 interface while the top a-Si layer deposited at higher temperature could nucleate with a smaller number of nucleation sites. The incubation time and transformation behavior were determined by the deposition temperature of the top layer. As an example, the grain size of the double layer film deposited sequentially at 150 °C and 200 °C enhanced to 1.8 μm while that of the monolayer film deposited at 200 °C was 1.4 μm.

This paper presents the results of low temperature deposition of poly-Si films deposited on SiO2 layers. Hydrogen dilution, hydrogen atom treatment, and hydrogenation of the SiO2 surface steps were applied to deposit the Si films. The above treatment steps were usually used in the plasma enhanced chemical vapor deposition and they were extended to be used in the electron cyclotron resonance chemical vapor deposition to identify the grain growth effects. The nucleation and microstructure of the silicon films were observed by cross-section transmission electron microscopy (XTEM).

High purity amorphous silicon layers were obtained by ultrahigh vacuum (millitorr range) chemical vapor deposition (UHVCVD) from disilane gas. The crystalline fraction of the films was monitored by in situ electrical conductance measurements performed during isothermal annealings. The experimental conductance curves were fitted with an analytical expression, from which the characteristic crystallisation time, tc, was extracted. Using the activation energy for the growth rate extracted from our previous work, we were able to determine the activation energy for the nucleation rate for the analysed-films. For the films including small crystallites we have obtained En ∼ 2.8 eV, compared to En ∼ 3.7 eV for the completely amorphous ones.

The polysilicon thin film transistor has been actively studied for the large area display applications like active matrix liquid crystal displays and for load cell in static random access memories. Due to low effective carrier mobility in polysilicon, the circuit speed is limited. Since the circuit delay time is directly proportional to the square of the channel length, short channel TFTs will be advantageous for high speed applications. In this work, we have studied the current voltage characteristics of an inverted sub-micron P-channel polysilicon thin-film transistor with self-aligned LDD structure to obtain a well-controlled channel and drain offset lengths. The particular features we examined are the leakage current and mobility. The leakage current and the ON current were found to be in the picoamp and micro-amp range respectively for devices having channel length in the range of 1.0μm to 0.35μm. Even very small devices having L&W = 0.35μm × 0.35μm exhibited characteristics similar to wider devices. The on/off current ratio was in the order of 105 before hydrogenation.