193-nm excimer laser-assisted etching of polysilicon was studied in vacuum and in the presence of Ar, CF3 Br, CF2 Cl2, and NF3. In inert atmospheres (vacuum, Ar) exposure to the laser led to jagged profiles at high fluences (>350 mJ/(cm2-pulse)) resulting from surface temperature gradients. At lower fluences, a resolidified Si-SiO2 lump was formed by thermal and surface tension gradients induced by laser heating. In the presence of 193-nm radiation, CF3Br showed some propensity to etch polysilicon, while CF2Cl2 did not show any appreciable etching.

Etch experiments were also performed in the presence of NF3 Maximum etch rates of 0.6 A/pulse were obtained for pressures greater than 500 torr and fluences exceeding 200 mJ/(cm2-pulse). An adsorptive etch mechanism is proposed, where NF3 molecules diffuse to the surface, adsorb and then react after absorbing laser radiation. Etching of micron profiles in polysilicon was also examined.

The use of CHF3 plus oxygen plasma to achieve selective and anisotropic patterning of SiC thin films in the reactive ion etching (RIE) mode is reported. Experiments were performed using various levels of oxygen percentage (from zero to 90%), pressure (from 20 to 300 mTorr) and power (from 100W to 350W). Anisotropic etching of SiC with a vertical-to-lateral etch ratio in excess of 8:1 was measured for a CHF3 + 75%02 mixture at 20mT pressure and 200W RF power. Under these conditions, the SiC etch rate was measured to be 400 A/min and the selectivity over Si was approximately 2.2:1. The effect of the cathode DC potential and emission intensity of various species in the plasma on the SiC and Si etch rates is considered.

Reactive ion etching induced damage in GaAs and Al0.22Ga0.78As was studied using Raman spectroscopy. The phonon spectra of undoped materials allow evaluation of damage to the crystal lattice and the coupled plasmonphonon spectra of n-type material provide a sensitive probe of electrical characteristics. Studies were made of layers exposed to plasmas of Ar, SF6 and SiCl4. Conditions for low damage Ar plasma cleaning and for dielectric cap removal by SF6 were established. Etching in the SiCl4 plasma generally produced strong damage, although low damage etching was observed in a few cases.

We have used a variety of characterization techniques including electron spin resonance (ESR), photothermal deflection spectroscopy (PDS), ellipsometry, and I–V and C-V analysis to study silicon samples damaged by 500–1500 eV Ar ions from a Kaufman ion source. In agreement with our ballistic penetration calculations, PDS and ellipsometry data show that the majority of the lattice damage lies within 40Å of the surface. The ellipsometry results are well modelled as a thin, damage-induced layer of a- Si with a high (4.63) refractive index, while the PDS measurements show an Urbach-like subgap adsorptance tail. In addition to Schottky barrier height alterations produced by Ar bombardment, we also observe marked changes in electrically active dopant densities in boron doped silicon samples. C-V analyses show that these changes extend quite far (1–2 μm) into the sample and are readily removed by a mild (150°C) thermal anneal. Hydrogen, injected from surface adsorbed H2O or hydrocarbons, appears to be the source of these effects. We will also discuss our upper limit estimate of 1013 “dangling bond” spins/cm2 for our damaged samples in light of prior ESR observations on similarly treated surfaces.

Reactive sputter etching of SiO2 in a low-pressure CF4 -O2 plasma has been investigated using a Langmuir probe to determine ion fluxes to the substrate and optical actinometry to monitor the concentration of F atoms, [F]. Etch yields Y, i.e. the number of substrate atoms removed per impinging ion, are obtained vs O2 composition and vs pressure. At constant pressure Y decreases slightly, but [F] increases considerably, with increasing O2 content. On the other hand, at constant O2 composition both Y and [F] increase strongly with increasing pressure. These results suggest that at low [F], relative to the ion flux to the substrate, the dominant etch mechanism is direct reactive ion etching, with the ions themselves as the main reactants, whereas at high [F] the overall etching is ion-enhanced, with F atoms as the main neutral reactants.

Monocrystalline ß-SiC (100) thin films were dry etched in CF4 and NF3 by reactive ion etching (RIE) and in SF6 by plasma etching. The etched surfaces were characterized by Auger Electron Spectroscopy (AES) and Scanning Electron Microscopy (SEM). The use of a stainless steel or an anodized Al cathode during RIE created a roughened SiC surface, which was contaminated with Fe or Al2 O3respectively. The roughness was caused by a micromasking effect produced by the deposition of these contaminants. By contrast, a carbon cathode yielded a very smooth and a much cleaner etched surface. Plasma etching of SiC in SF6 resulted in a very rough surface, but the AES spectra indicated almost no contamination and very little native oxide or fluorine. The optimal condition for etching SiC was determined to be RIE in NF 3 on a C cathode.

Reactive ion etching of Al( ≤ 4 wt.% Cu) and AI(Cu)/W films is described. Using single layer resist, 1 μm lines are demonstrated over 0.3 μm topography in the bilayer films and 0.5 um lines in the single layer layer films over planar surfaces. For Al alloys with Cu concentration in the ranges 2–4 wt.% it is found that clean etching is strongly dependent on deposition condition. A model is proposed to explain this.

Using photoluminescence we investigate defects introduced into silicon by ion beam etching. The luminescence spectra show the presence of various defects known from radiation damage studies. Ion-beam milling with different noble gas ions produces a family of defects which gives rise to almost identical photoluminescence spectra. The intensity of the Ar noble gas defect luminescence is studied for different ion-beam energies (200–2000eV) and crystal orientations. The threshold energy to create this defect leads to a model of the defect structure.

Al/p-Si Schottky barriers formed on wafers implanted with 10–20 keV Ar exhibit low-temperature electrical properties characteristic of grain boun1dary transport Subsequent low-energy (0.4 keV), high fluence ( ∼ IOE18 cm−2) H implant is found to passivate the grain boundaries of the Ar implant-induced microcrystals. Extremely high Al/p-Si Schottky barrier heights are obtained following the dual implants, and deep level transient spectroscopy (DLTS) measurements reveal that H also alters the properties of traps introduced by the Ar implant, thus improving the diode characteristics.

A computer modeling method was used to study various factors such as the etch time, the degree of planarization of the sacrificial layer, the original surface shape of the sacrificial layer, the etch ratio, and the original oxide step shape, that directly affect the topography of an etchback planarized surface.

Multi-layer resist has been utilized commonly in optical and E-beam lithography for its ability to resolve submicron feastures over topography. In addition, the use of a low-Z(atomic number) material as the intermediate layer reduces the proximity effect. This paper describes the development of etching process used to pattern a tri-level resist based on polyimide, an inorganic intermediate layer, and positive resist as top image layer. A highaspect-ratio image can be anisotropically transfered from the inorganic intermediate layer into the polyimide planarizing layer by oxygen RIE. Directionality, profile control, and backsputtering residue are the primary considerations during the pattern transfer etching. The influence of pressure, power and self-bias voltage on the etching process are described. The residue is caused by sputtering of the electrode material and the etch barrier material. Backsputtering residue from electrode can be prevented by covering all exposed conducting surfaces with an organic dielectric material, in this case an ardel plate. Etch residue contributed by the intermediate layer is quantified according to its pattern density and the influence of the pressure. Sidewall profiles and their relationship to planarizing layer thickness are also discussed.

Nickel and doped polysilicon lines can be written at speeds exceeding 1000 microns/sec using laser direct-write deposition. We explore the roles of gas pressure, composition, and laser power in determining writing speed and line morphology. The use of a surface layer of amorphous silicon provides optical absorption, thermal and electrical insulation which help to maintain high, relatively stable, surface temperature.

Laser direct-write deposition is used to interconnect CMOS gate arrays by means of computer controlled laser pantography. Complex circuits, such as an array of five 16-stage shift registers and one 16-stage counter have been successfully fabricated and tested.

In this paper, comparisons of material and electrical parameters between qate and interpoly dielectrics consistinq of thermal oxides, nitrides, nitrided oxides and oxidized nitrides are reported. A range of dielectrics, 5 nm to 30 nm thick, are thermally grown using a matrix of oxidation cycles, ammonia concentration and nitridation temperatures and pressures. Fabrication of polysilicon gate and interpoly capacitors is typical of industry standards. AES, RBS and ellipsometric analysis of dielectric material properties are discussed and electrical characterization results are presented.

Point defects caused by common fabrication methods may increase device susceptibility to radiation or hot carriers. In this study, defects induced by dry and wet oxidation, ion implantation, and rapid thermal annealing are examined by electron paramagnetic resonance. A brief 02 anneal at 900°C is found to be more effective than N2 in transformation of a steam-grown oxide interface to that of a dry oxide. A N2 anneal at 450 °C has little effect, and must be extended to about 2 hr to dessicate the interface. Implants of B, P, and BF2 have no direct effect on the interface, but activation anneal in N2 at 900°C produced large Pb concentration. Implant generates E′ centers in the oxide, which are eliminated by the activation. Rapid thermal annealing below 600°C reduces interface traps, but increases them above 700°C, with severe oxide and interface damage at 1100 °C. Electron-beam lithography and plasma- or ion-beam etching are discussed briefly.

CVD tungsten has been under active investigation as a contact barrier, as a material for contact fill and via fill, and as an interconnect metal for VLSI applications [1].

Thermal stability of W/WSix/Si (X=1.4, 2.1, 2.5) contact structures has been characterized at annealing temperature up to 900°C. Thermal reaction in these contact structures was strongly affected by the X values of deposited WSix films. The X values were presicely controlled by a novel co-sputter deposition apparatus. After annealing at 900°C, in the samples of X=1.4 and 2.1, the W films were stably maintained. On the other hand, in the sample of X=2.5, the structure changed into the WSi2. 2/Si resulting in the disappearance of the W film. The silicidation of the W film in the sample of X=2.5 was likely due to a diffusion of Si into the W film through the precipitated region of the excess Si in the tungsten silicide film. The W/WSi2.2/Si structure can provide the electrically stable W-Si contact at annealing temperature up to 800°C.

Ultrathin silicon dioxide films, 5 nm thick, were grown in a double-walled furnace at 850°C in dry O2. A consistent improvement in the electrical properties is observed following the oxidation either with a Post-Oxidation Anneal (POA) at 1000°C in N2 or with the same POA followed by a short re-oxidation (Re-Ox) step in which 1 nm of additional oxide was grown. We attribute these results to the redistribution of hydrogen and water related groups as well as to a change in the concentration of sub-oxide charge states at the Si-SiO2 interface. A further improvement observed after the short re-oxidation step had been attributed to the filling of the oxygen vacancies produced during the POA. High resolution Transmission Electron Microscopy cross-sectional observations of the Si-iSO2 interface have evidenced an increase in the interface roughness after the thermal treatment at high temperature. These results are in agreement with recent XPS data.

The characteristics of RF bias-sputtered Al films are clarified. A negative substrate bias voltage, VDC, produced by RF biasing, strongly influences not only the planarization effect but also film characteristics such as hillock and void growth, and Ar content.

Films deposited at VDc lower than -150 V. are significantly degraded due to the formation of two kinds of voids grown during annealing. One type is a blister-like voids, while the others are large and irregular. These are produced when Ar is released from the films during heat treatment. as evidenced by the fact that the amount of Ar released from the films rapidly increases when VDC is lower than -150 V.

Although biasing strongly effects Al films resulting in the formation of an almost complete (111) texture. the effect degrades as VDC exceeds -200 V. Thus, Al bias sputtering requires a high resputtering rate and a VDC higher than -150 V to achieve appropriate planarization with suitable film characteristics.

A RIE process has been developed for the etching of 0.5 μm CMOS Polysilicon gates defined using both E-Beam direct writing and sub-micron optical lithography. Profile control and selectivity were enhanced by using a two-step pattern transfer process wherein the Photoresist mask was used to define a thin Silicon Nitride layer which was subsequently used to define the underlying Polysilicon gate electrode. High etch selectivity to both the Silicon Nitride mask and the thin gate oxide was achieved using a Cl2 plasma chemistry after a BCl3 initiation step. The effect of BCl3 initiation on the poly profile and the effect of loading on profile and selectivity will be presented.

An experimental study of dopant diffusion at Si3N4 and SiO2 film edge is reported. The results show that an alternation of enhanced and retarded diffusion of both As and Sb at the Si3N4/SiO2 film edge was observed after 1100°C heat treatment in N2. The observed effect has been correlated to the alternation of tensile and compressive stress field at the film edge for the first time. Additionally, the different shape of junction profile of As and Sb seems to be a result of impurity misfit strain effect. From this experiment, it is obvious that the interaction of film edge stress fields will make the control of dopant profile more difficult for smaller window width. Hence the film edge effect should be taken into account especially for the fabrication of submicron devices.