Multi-layer devices based on thin films in Large Area Electronics have different intrinsic and extrinsic properties that must be optimised to produce the correct physical shape of the device, in addition to having acceptable electrical characteristics. For instance it is quite easy to produce individual layers optimised for electrical performance that will physically “pull off’ underlying films, or result in poor step coverage. The factors that must be considered include mechanical stress, etching rates and profiles, thickness and stoichiometry uniformity, and thermal budgets, as well as electrical characteristics. This paper gives an example of silicon nitride optimisation for use in a-Si:H TFT projection displays. Three different silicon nitride layers were included to give a storage capacitor, together with controlled etch profiles for step coverage. The layers were optimised with respect to several different parameters in the minimum number of depositions by the use of experimental design techniques.

We fabricated the high performance a-Si:H TFT using the N2 plasma treated APCVD SiO2 as a gate insulator. The effects of N2 plasma treatment on the APCVD SiO2 were investigated by XPS and SIMS Measurements. And the formation of the oxynitride interface layer between a-Si:H and APCVD SiO2 was found in the a-Si:H TFT. From our experimental results, It May be concluded that most nitrogen atoms, which were incorporated by the exposure of SiO2 layer to N2 plasma, exist, not bonded to other atoms, near the surface of the SiO2 layer and during the sequential deposition of a-Si:H on the N2 plasma treated APCVD SiO2 layer Si-N bonds are formed, resulting in the oxynitride layer in the interface region. This explains the high performance a-Si:H TFT with the N2 plasma treated APCVD SiO2 gate insulator.

The combination of a-Si low leakage pixel TFTs with poly-Si TFTs in peripheral circuits provides an excellent method for reducing the number of external connections to large-area imaging arrays and displays. To integrate the fabrication of the peripheral poly-Si TFTs with the a-Si pixel TFTs, we have developed a three-step laser process which enables selective crystallization of PECVD a-Si:H. X-ray diffraction and transmission electron microscopy show that the polycrystalline grains formed with this three-step process are similar to those crystallized by a conventional one step laser crystallization of unhydrogenated amorphous silicon. The grain size increases with increasing laser energy density up to a peak value of a few Microns. The grain size decreases with further increases in laser energy density. The transistor field effect mobility is correlated with the grain size, increasing gradually with laser energy density until reaching its maximum value. Thereafter, the transistors suffer from leakage through the gate insulators. A dual dielectric gate insulator has been developed for these bottom-gate thin film transistors to provide the correct threshold voltages for both a-Si and poly-Si TFTs.

This research addresses silicon nitride dielectrics for a-Si:H TFTs. Si-Si bonds in these films detected by AES have been identified as the major factor that degrades the performance of the TFTs. With no detected Si-Si bonds in the silicon nitride and a relatively low concentration of Si-NH bonds, the TFTs show optimized performance.

The effects of top-insulator on the instability problems of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been studied. In a-Si:H TFT with top-insulator (E/S type), charge trapping into the both of top-insulator and gate insulator has been shown under the bias stress.

In order to investigate the charge trapping effects of top-insulator, we proposed a new method of Measurement. By this Method, we observed that trapped charges in top-insulator increased drain currents for positive gate bias stress, and this increment of drain currents was more serious with increasing the ratio of source/drain overlap length to channel length. It has founded that the instability problems of a-Si:H TFTs was attributed to the effects of top-insulator as well as that of gate insulator.

We have investigated the stability of the hydogenated amorphous silicon thin film transistors (a-Si:H TFTs) employing silicon dioxide (SiO2) with N2 plasma treatment as a gate dielectric, where SiO2 was deposited by atmospheric pressure chemical vapor deposition (APCVD). Their stability was compared with those of a-Si:H TFTs whose gate dielectric was silicon nitride (SiNx) deposited by plasma enhanced chemical vapor deposition (PECVD). Two kinds of stresses, gate bias and light illumination, were applied. The threshold voltage shin (AVu,) and the inverse subthreshold slope shift (ΔVth) were measured as a function of the bias voltage and the light stress time. For the positive bias stress, the ΔVth, of the a-Si:H TFTs with the N2 plasma treated SiO2 dielectric is smaller than that with the PECVD SiNx gate dielectric. For the negative bias stress and light stress, however, the ΔVth of TFT with N2 plasma treated SiO2 dielectric is larger than that with the SiNx dielectric

A novel method to derive the output characteristics of a-Si:H thin film transistors from the channel conductance curve is presented. The Method well reproduces the experimental data both in the linear and saturation regimes without using any adjustable parameter. The Method is simple and fast enough to be used in a circuit simulator.

AMorphous silicon thin film transistors may be manufactured using a variety of gate insulator Materials. The sign and magnitude of the fixed charge, Qf, in the gate insulator material determines the as-deposited density of states in the a-Si:H as predicted by the defect pool Model [1]. For the case of PECVD nitride Qf is positive giving rise to a defect peak in the lower part of the bandgap. In thermal oxide, which has small negative Qf the states are in the upper part of the bandgap. Using the technique of low temperature bias stress or high temperature bias anneal it is possible to create further defects in the bandgap on top of those already present, facilitating the study of upper (Dh) and lower (De) gap states. In a previous work we studied the removal kinetics of such defects using TSDR (Thermally Stimulated Defect Removal) in both PECVD nitride and thermal oxide devices [2]. Here we repeat the experiments on thin film transistors made with PECVD helium diluted oxide as the gate insulator Material. PECVD helium diluted oxide is interesting as its Qf May be varied during Manufacture. Thus TFTs with characteristics similar to either thermal oxide or PECVD nitride can be obtained.

High electron Mobility (over 3 cm2/Vs) thin film transistors (TFTs) have been fabricated using a-Si:H on thermally oxidized crystalline Si substrate. The procedures for fabricating the high performance TFTs are presented and the possible reasons for the high mobility are discussed.

We have measured the current-voltage characteristics of amorphous silicon thin film transistors (a-Si TFTs) over a wide range of temperatures (20 to 160°C) and determined the activation energy of the channel current as a function of gate bias with emphasis on the leakage current and subthreshold regimes. We propose a new method for estimating the density of localized states (DOS) from the dependence of the derivative of activation energy with respect to gate bias. This differential technique does not require knowledge of the flat-band voltage (VFB) and does not incorporate integration over gate bias. Using this Method, we have characterized the density of localized states with energies in the range 0.15–1.2 eV from the bottom of the conduction band and have found a wide peak in the DOS in the range of 0.8–0.95 eV below the conduction band. We have also observed that the DOS peak in the lower half of the bandgap increases in magnitude and shifts towards the conduction band as a result of thermal and bias stress. We also measured an overall increase in the DOS in the upper half of the energy gap and an additional peak, centered at 0.2 eV below the conduction band, which appear due to the applied stress. These results are in qualitative agreement with the defect pool Model [1,2].

The effects of bias-stressing n- and p-channel thin-film transistors, employing thermal silicon dioxide as gate insulator, have been analysed by using different techniques, including field-effect, space-charge photomodulation and photo-induced discharge. Photo-induced discharge experiments have pointed out as parasitic resistance effects can be present in p-channel devices. In order to reduce this problem, thin active layer p-channel devices have been fabricated and, combining these results to those relative to the n-channel transistors, we deduced a predominance of charge injection at low and moderate stress-biases while at high-stress biases modifications in the density of states take place.

The origin of contact resistance in a-Si:H TFTs is investigated by formulating a model for the contact limited current. The Model accounts for the independent contributions of the Metal–n+a-Si:H interface resistance and the space charge limited conduction through the intrinsic a-Si:H film. Using our contact current model we investigated the I–V behavior of an n–i–n structure with a thin a-Si:H layer (=700Å) and found that the resistance of the Metal–n+a-Si:H interface is nonlinear. We incorporated the contact limited current expression into a full TFT Model and simulated the TFT performance for a wide range of Metal–n+a-Si:H interface resistance values and intrinsic a-Si:H film thicknesses. We found that the Metal–n+a-Si:H interface resistance dominates over space charge limited conduction for the thicknesses of intrinsic a-Si:H films used in AM-LCD switches. This trend is sustained even when the effective resistance of the Metal–n+a-Si:H interface decreases due to the nonlinear current conduction across it.

A novel α-Si(C):H color sensor array has been developed. In this device a single pixel consists of a combination of an amorphous silicon nipin detector and a crystalline operational amplifier. Steady state and transient opto electronic behavior of the nipin structure have been studied in order to optimize the design of the image sensor. Nipin structures are found to exhibit excellent dynamic range (125 dB) and linearity. The crystalline electronics causes only very little signal distortion which makes this sensor device a potential candidate for color image capture and processing for a wide range of illumination levels.

An effort has been made to improve the brightness of the a-SiC:H Thin Film LED (TFLED) by using highly-thermal conductive Metal (SUS) sheet substrates instead of glass substrates. The structure of the TFLED is metal substrate/n a-SiC:H/i a-SiC:H/p a-SiC:H/ITO. The results from the preliminary examination show that at room temperature; 1) the threshold current necessary for the observation of the emission for the TFLED deposited on a SUS substrate is half of that for a glass substrate, 2) the highest brightness is about 5 cd/m2 for a SUS substrate while about 1 cd/m2 for a glass substrate.

The development of a large area, high-resolution, a-Si:H x-ray imager is reported. The array has 1536×1920 pixels, a pixel pitch of 127μm, and an area of 19.5×24.4 cm2. Tne array is tailored to the high frame rate and high spatial resolution requirements of diagnostic x-ray imaging. The design of this array is presented and examples of x-ray images are illustrated. Initial Measurements of the sensor capacitance and pixel time constant properties are in good agreement with theoretical expectations. These results indicate that high-resolution arrays of this construction are capable of providing fluoroscopic images at rates of at least 30 frames per second.

Both total electroluminescence intensity and spectrum have been measured as a function of applied voltage at various temperatures on p-i-n devices with i-layer thickness from 0.2 μm to 2.0 μm. At constant temperature the luminescence intensity shows a power-law dependence on forward bias current with an exponent, γ. As the temperature increases from 80 K to 300 K, γ decreases from 1.5 to 0.9 in thin (≤ 0.5 μm) samples. Thick, 2.0 μm, samples on the other hand, show γ ≈ 1 over the same temperature range. Each electroluminescence spectrum has been decomposed into two gaussian functions corresponding to the main band and the defect band luminescence, respectively. We find that the integral intensity of the high energy luminescence band versus the current obeys a power-law with exponent γ1, while the integral intensity of the low energy luminescence band versus the current obeys a power-law with exponent γ2· γ1 > γ2 for all samples at all temperatures in these Measurements.

A TFA image sensor consists of an amorphous silicon based multilayer structure on top of a crystalline ASIC. The Multilayer acts as the optical detector, whereas the ASIC performs analog or digital signal processing for each individual pixel. Depending on the operation Mode, the dynamic range of the detector exceeds the performance of conventional CCDs by far. Pixel electronics which is adapted to the requirements of the detector can thereby maximize the dynamic range of the complete sensor array. Crosstalk among adjacent pixels can be eliminated by technological or electronic Means.

We describe the performance of an amorphous silicon imaging system designed for high speed (>10 frames/sec) scanning of a document. The system comprises a new page-sized sensor array with 1536×1920 pixels, an illumination source, and the readout electronics. With appropriate color filters, one can achieve color imaging of a document without the registration problems associated with linear scanners. We describe the color imaging properties and discuss how the color response, sensitivity and uniformity depend on the properties of the amorphous silicon sensors.

With the possibility to deposit thick amorphous silicon layers, applications like particle- or X-ray detectors can be envisaged. The present paper describes new results obtained with a series of thick p-i-n diodes produced by VHF-GD (Very High Frequency Glow-Discharge). The goal is to obtain the maximum output signal for given detection conditions (reverse voltage, generation rate,…). The problem of the collection of the electrons and holes is discussed in this paper, in relation with the distribution of the electric field. As is well known, trapped charges screen the inner part of the intrinsic layer of the detector. Due to this effect, even under strong reverse bias-voltage, a complete depletion of the whole intrinsic layer can in general not be obtained for thick diodes; however, even if the diode is not completely depleted, the signal increases with increasing diode thickness until a maximum is reached for the signal, and then it decreases again. Finally, different rise-times of the transient current (current after a jump in bias voltage is applied) have been Measured. Differing between one diode and the other, the rise-time of the transient current was found to vary between 0.1 seconds and 1 hour; a clear dependence on the deposition conditions is observed. Long rise-times are major difficulty to be removed, because most of the applications like imaging require short response time of the detector.

We present a novel family of photodetectors based on hydrogenated amorphous Si/SiC p-i-n-i-p heterostructures. Front p-i-n and rear n-i-p diodes work one as a detector and the other as a load impedance, depending on the polarity of the applied voltage. Due to different absorption at different wavelengths, the devices operate as bias-controlled light detectors in either the blue or the red regions. The energy gap and the thickness of the two intrinsic layers have been optimized to obtain a sharp wavelength selection (centered at 430 and 630 nm) with high rejection-ratios and good quantum efficiencies. The I-V characteristics and the device time response are investigated and simulated by SPICE.