A two-channel optical-fiber pyrometry technique for simultaneous measurement of thermal radiance and emittance was used to measure and control the temperature of silicon wafers heated by quartz-halogen-tungsten lamps in various rapid-thermal processors, including an A.G. Associates Heatpulse. The ripple method dynamically determines emittances by sensing time-dependent components in radiation from the lamps and radiation reflected by the wafer surface. Wafers were coated with films of various textures and patterns to test the technique over a range of surface emittances spanning about an order of magnitude. Temperature accuracies of at least ±5°C are achievable from 650°C to 1050°C, and above, for pyrometry at lμm wavelength.

This paper reviews the current status, problems and options in RTP system and process design. Some commercial systems will be discussed along with some improvements that can still be made in temperature reproducibility, process control and yield. This includes some recent developments in temperature reproducibility by compensated emissivity control.

Uniformity issues regarding temperature and process gas hydrodynamics are highlighted in relation to reactor design. Especially in CVD applications, where radiative heat transfer may not longer dominate convective and conductive heat transfer, modeling and visualization of gas flow patterns are becoming increasingly important. Here, reactor design should be such that a laminar flow regime is reached without turbulence and without chemical memory effects upon switching to other gas compositions. Some flow visualization results are illustrated.

Some new options for micro- and nanocrystallization reactions are presented before we conclude with a technology roadmap to the 1-Gbit era.

A new RTP system concept is proposed and demonstrated. The system uses a vertical cylindrical quartz tube, while the wafer is placed horizontally. Linear halogen lamps are arranged in an hexagonal shape. Optimal power control results in a temperature difference within ±1.5 °C over a 6 inch wafer in steady state. Oxidation under optimal conditions results in a 1.37% standard deviation for an average oxide thickness of 110.4 Å. The temperature nonuniformity during the transient has been greatly improved by using dynamic control. The main advantages of this new system concept are its excellent temperature uniformity and the good accessibility of the wafer for technological treatments and in situ measurements.

For Rapid Thermal Processing one of the essential problems is the dynamical temperature controlling to reduce temperature nonhomogeneities during heating up and cooling down, which are responsible for layer nonhomogeneities and slip generation. A pyrometer row consisting of five sensors is used for temperature distribution measurement in radial direction, which allows to investigate the dynamical behaviour during the heating cycles. Together with a developed software tool, which is suitable for calculation of the dynamical temperature distribution across the wafer under process conditions where the convective heat losses can be neglected, the influence of heating-up velocities is investigated. The obtained results show that in a scalar controlled system process conditions optimized for steady state lead to maximum temperature nonhomogeneity during the heating-up period, due to the changing heat balance in the system.

The goal in Rapid Thermal Processing is the realization of homogeneous and stable temperature distribution across the wafer.

Due to the wafer edge an additional heat loss occurs, which leads to temperature decrease near the wafer boundary. This can be the origin for layer thickness inhomogenities and defect generation. For successful compensation it is necessary to know why such a temperature gradient exists.

The heat transfer at the wafer edge was investigated by using computer simulation.

The results confirmed by experimental data in the pressure range of 1.. 760 Torr are discussed and criteria for the compensation of the temperature gradient near the wafer edge are developed.

The next five to ten years will show a dramatic increase in the number of sensors and actuators in use. Several advances in technology, namely integrated sensors, fast reliable communications, and powerful computers, are making such changes possible. Coordinating the complex interactions of multiple sensors and control settings can be too confusing for an ad-hoc approach. Applying modern model-based control theory to multi-input/multi-output systems has the potential of improving the yield and throughput in a computer integrated manufacturing environment.

Our expectation is that as more sensors and actuators become available, it will be important to handle internal communications between processing subsystems in a uniform manner to allow for incremental expansions to the processing equipment. Because of the wide assortment of physical sensors available for control equipment, an architecture is presented which attempts to unify the communications and control in a multiprocessor environment. The focus of this paper will be to explain one method of controlling a Rapid Thermal Multiprocessing chamber and how it is designed to handle future growth.

The implementation and experimentation are being performed on the Rapid Thermal Multiprocessor (RTM) at the Center for Integrated Systems (CIS) at Stanford University.

Single wafer rapid thermal processing (RTP) is emerging as a key player in the processing of advanced sub-half micron memory devices. The high temperature processing of large diameter silicon wafers can create sufficient thermal stress for generation of dislocation, slip, and gross mechanical instability of the wafer. The aforementioned factors may lead to loss of device yield, dielectric defects, and reduced photolithographic yield due to degradation of virtual wafer flatness. Moreover, the loss of geometrical planarity of wafer due to warpage can make it impossible to process a wafer or can lead to self-fracture of the wafer.

In this paper we present the warpage and stress results of our study on plain and patterned structures that were subjected to RTP at different stages of the CMOS process flow. Experimental results have been gathered with full wafer scanning technology using non-contact capacitive probes to measure more accurate global stress values. The stress and warpage values on the patterned wafers could be measured accurately without any light scattering effects and destructive interference. It is reported that the thermal processing creates significant variations in shape change around the wafer which could be identified using the full wafer data set acquired using this evaluation technique. We have successfully tracked variations in film stress for both plain and patterned structures as a cumulative effect and correlated it with the overall wafer warpage. The effects of incoming wafer warpage, ramp rate in RTP, and high stress nitride films on the overall wafer warpage are also reported.

We present finite element simulations of fluid flow, heat transfer, and chemical reactions in axisymmetric rapid thermal processing (RTP) configurations. A new approach to simulating radiation heat transfer between lamps, substrates, and system walls is described. The method accounts for multiple reflections and readily allows the inclusion of temperature, radiation wavelength, and materials specific emissivity parameters. The influence of system geometry, lamp power profile, substrate and wall emissivity parameters, and process gas flow upon RTP performance characteristics is illustrated through examples. Transient flow and heat transfer simulations are used to identify operating conditions where flow recirculations are avoided. The further use of physically based models in the design and optimization of RTP systems is discussed.

A 3-dimensional model of an industry standard Rapid Thermal Processing (RTP) chamber (AG Assoc. 4108 Heatpulse) has been created. The chamber consists of a quartz sleeve containing a 200mm wafer surrounded by a polysilicon thermal guard ring. The wafer is heated by tungsten filament lamps which are assumed to radiate according to Boltzmazi' gray-body model. Detailed radiation transfer among ∼4000 finite surfaces is considered as well as Navier-Stokes solution of an energy balance to determine chamber temperature distributions.

Experimental wafer temperature distributions have also been obtained using an 8 inch wafer imbedded with 17 thermocouples and from oxide growth measurements at 700 and 1100 Centigrade respectively. The model predictions are within 1% of the experimental data at both low and high temperatures with the only parameter being the lamp filament temperature. The model is used to demonstrate the ability to examine non-symmetric effects of varying specific chamber properties (i.e. lamp power output, wall reflectivity), as well as transient phenomena.

The individual film thicknesses of multilayered structures processed by rapid thermal processing are of the same order as the wavelengths of the incident radiation. This induces optical interference effects which are responsible for the strong dependency of surface reflectivity, emissivity, and temperature distributions on the geometry of the layering structures, presence of patterns, and thickness of the films. A two-dimensional, finitedifference numerical model has been developed to investigate this microscale radiation phenomena and identify the critical processing parameters which affect rapid thermal processing of multilayer thin films. The uniformity of temperature distributions throughout the wafer during rapid thermal processing is directly affected by incident heater configurations, ramping conditions, wafer-edge effects, and thin-film layering structure. Results from the numerical model for various film structures are presented for chemical vapor deposition of polycrystalline silicon over oxide films on substrate. A novel technique using an edge-enhanced wafer which has a different film structure near its edge is presented as a control over the transient temperature distribution.

With the ability to perform heat cycles on a wafer quickly and within low thermal budgets, Rapid Thermal Processor (RTP) systems offer potential advantages over conventional furnaces. However, RTP' have an inherent problem with wafer temperature uniformity which can cause process nonuniformity and wafer stress.

In this work, a thermodynamic model of a wafer is used to form an understanding of the wafer heating problem. This model shows that an idealized heating flux density profile can maintain thermal uniformity at steady-state temperatures. This profile uniformly heats the wafer while counteracting the additional cooling at the wafer edge. However, this profile induces temperature nonuniformities during wafer temperature transients, such as overheating of the edge during temperature rises. Therefore, a dynamic flux-density profile is needed during temperature transients to ensure continuous temperature uniformity. The model is used to predict the steady-state and dynamic profiles required to process a wafer with complete temperature uniformity. The predicted profiles can be used to adapt an RTP chamber and control system to approach production of uniform wafers and also for the design of new systems. This paper will explain the theory of wafer heating, describe the dynamic profiles required for continuous uniformity, review the wafer model, show the result of an idealized profile for steady state and transients processing, and present a new control methodology to achieve uniform temperatures.

Modeling and simulation of rapid thermal processing has been studied extensively in the past. This work presents the results of a combined simulation and measurement study of a commercial multilamp RTP chamber. The simulations were used to estimate the contributions of different geometrical, material, process, and physical effects on temperature uniformity. The physical effects considered in the simulations included radiation, thermal conduction, transient effects during ramp up and cool down and the effects of patterns on the wafer surface. The effects were corroborated by direct temperature measurements using thermocouple embedded wafers, and the results were used to reliably calculate stress effects. The stress distributions were determined analytically in cases without surface films on the wafer. In the case of wafers with surface films, stress distributions were calculated based on thermal strains. This study allows us to concentrate efforts on increasing temperature uniformity to those areas where the greatest benefits in terms of yield and film uniformity can be obtained.

The measurement of the sheet resistance of Arsenic implanted layers is almost exclusively used for the monitoring of temperature nonuniformity of RTP equipment. However, as is shown in this contribution this technique relies on several averaging processes and a satisfactory uniformity of sheet resistance achieved on the implant monitor does not mean that the same performance will be achieved on the wafer with different optical properties. The sheet resistance uniformity is not the only the function of the processing temperature but also the function of the processing parameters such as annealing time, rate of heating and cooling, intensity of radiation and its spectral variation as well as function of the optical properties ofthe processed material. Impact of the substrate on the achieved results and processing dependence are discussed.

We report a systematic study of dopant diffusion behavior for thin gate oxides and polysilicon implanted gate structures. Boron behavior is emphasized and its behavior is compared to that of As+ and BF2+. Dopant activation is achieved by rapid thermal annealing. Test structures with 100 Å, 60 Å and 30 Å gate oxides and ion implanted polysilicon gate electrodes were fabricated and characterized after annealing by SIMS, SEM, TEM, and C-V rpeasurements. For arsenic implanted structures, no dopant diffusion through a gate oxide of 30 Å thickness and an annealing condition as high as 1 100*C/1Os was observed. For boron implanted structures, as indicated by SIMS depth profiling, structures annealed at 1000*C/10s exhibit a so-called critical condition for boron diffusion through a 30 Å gate oxide. Boron dopant penetration is clearly observed for 60 Å gate oxides at an annealing condition of 1050 0C/10s. The flatband voltage shift can be as high as 0.56 volts as indicated by C-V measurements for boron penetrated gate oxides. However, 100 Å gate oxides are good diffusion barriers for boron at an annealing condition of 1100°C/10s. For BF2 implanted structures, the diffusion behavior is consistent with behavior reported in the literature.

The effect of fluorine preamorphization on boron diffusion and activation during rapid thermal annealing (RTA) has been investigated. Compared with low energy B or BF2 implant into crystalline Si, F preamorphization suppressed the transient enhanced diffusion of B and increased dopant activation. Results show that the tail diffusion was absent, and thus the junction depth of the RTA annealed sample was established by the as-implanted B profile. Secondary ion mass spectroscopy and cross-sectional transmission electron micrograph results show F accumulation near the surface and at end-of-range defects. The interaction of F with defects is believed to reduce the B diffusion during RTA.

The diffusion and activation of ion implanted boron and BF2 during rapid thermal annealing (RTA) was modeled by considering the reaction kinetics between point defects and boron. The diffusion model uses the Monte Carlo generated point defect profiles, an extended defect model and a surface amorphization model for high dose BF2 implantation. Excellent simulation results have been achieved by using a single set of diffusion and kinetic parameters to model the enhanced diffusion of boron during RTA for a wide range of B and BF2 implant doses.

In this paper, B diffusion in Si with BF2-implanted CoSi2 as a diffusion source has been studied using SIMS analysis. The concentration-dependent diffusivity of B in single crystal Si is obtained by Boltzmann-Matano analysis. The data show that the B diffusivity in single crystal Si is more than one order of magnitude higher than the published data where a conventional B diffusion source (BN or B2H2) is used. Anomalous concentration dependence of the B diffusivity in Si for ultra-shallow B SIMS profiles was also observed. Possible physical mechanisms which involve implant damage in the Si substrate, the generation of point defects such as Si vacancies and interstitials during silicide formation, and B-defect interactions are discussed.

Ion implanted CoSi2 as a gate doping source has been studied as a compatible process to the Silicide-As Diffusion-Source (SADS) process which has been widely considered for shallow source/drain junction formation. The effects of the polysilicon gate microstructure on diffusion behavior and the thermal stability of CoSi2 has been investigated. It has been found that CoSi2 formed on reoxidized polysilicon gates has poor thermal stability but requires short time to achieve degenerate doping near the polysilicon/gate oxide interface. On the other hand, CoSi2 formed on as-deposited amorphous silicon has excellent thermal stability but requires longer time to achieve degenerate doping near the polysilicon/gate oxide interface. The trade-off between the required thermal budget to achieve degenerate doping and thermal stability of the CoSi2/polysilicon gate structure will be discussed. In optimizing the process, our results indicated that reoxidized amorphous Si gates have both good thermal stability as well requiring short time to achieve degenerate doping. The thermal degradation of CoSi2 was found to have little effect on the gate oxide breakdown voltage.

The mechanism of the enhanced diffusion of boron during rapid thermal annealing (RTA) of BF2-implanted Si has been investigated, and a diffusion model is accordingly developed for a wide range of implant and annealing conditions. Simulation results are in excellent agreement with experiments for BF2 implant doses from 2×1013 to 5×1015cm−2, implant energies from 6 to 45 keV, and annealing temperatures from 950 to 1100°C. This model not only accounts for the transient enhanced diffusion due to the annealing of point-defect clusters and dislocation loops, but also for the retarded diffusion due to dopant precipitation. All the parameters used in this model are analytically determined.

Highly dense next generation dynamic random access memory (DRAM) devices impose severe restrictions on the times, temperatures and atmospheres of all thermal process steps following the sourcedrain implantation. BPSG reflow and source-drain implant activation are two of the process steps that contribute significantly towards enhanced overall thermal budget during the fabrication of DRAM devices.

In this paper, we present the results of an optimized thermal budget process using a combination of steam reflow and rapid thermal annealing (RTA). We demonstrate that this approach produces better reflow characteristics than the best RTA or reflow cycle alone. The processes will be compared on pchannel CMOS devices and the differences in various electrical characteristics will be highlighted. The results of BPSG reflow and dopant outdiffusion will be presented. Experimentally obtained data on junction depth from SIMS analysis will be correlated with corresponding RTA simulation results.