Hostname: page-component-cd9895bd7-gbm5v Total loading time: 0 Render date: 2024-12-22T02:28:37.101Z Has data issue: false hasContentIssue false
  • English
  • Français

Zr Oxide Based Gate Dielectrics with Equivalent SiO2 Thickness of Less than 1.0 nm and Device Integration with Pt Gate Electrode

Published online by Cambridge University Press:  14 March 2011

Yanjun Ma  and
Yoshi Ono
Yanjun Ma
Affiliation:
Sharp Laboratories of America, 5700 NW Pacific Rim Blvd, Camas, WA 98607
Yoshi Ono
Affiliation:
Sharp Laboratories of America, 5700 NW Pacific Rim Blvd, Camas, WA 98607
Get access

Abstract

ZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance ∼35 fF/μm2 with a leakage current of less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 611: Symposium C – Gate Stack & Silicide Issues in Silicon Processing , 2000 , C2.9.1
Copyright
Copyright © Materials Research Society 2000

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1] Kim, H.S., Gilmer, D.C., Campbell, S.A., and Polla, D.L., Appl. Phys. Lett. 69, 3860 (1996); S.A. Campbell, D.C. Gilmer, X. Wang, M. Hsieh, H. Kim, W. Gladfelter, and J. Yan, IEEE Trans. Electron Dev. 44, 104, (1997).10.1063/1.117129Google Scholar
[2] Sun, S.C. and Chen, T.F., Jpn J. Appl. Phys. 36, 1346, (1997).10.1143/JJAP.36.1346Google Scholar
[3] Momiyama, Y. et al. , Symp. VLSI Technology, p135 (1997).10.1109/VLSIT.1997.623735Google Scholar
[4] Park, D., Lu, Q., King, T., Hu, C., Kalnitsky, A., Tay, S., Cheng, C., IEDM Tech. Digest, p381 (1998).Google Scholar
[5] Guo, X., Ma, T.P., Tamagawa, T., Halpern, B.L., IEDM Tech. Digest, p377 (1998).Google Scholar
[6] Luan, H. F., Wu, B.Z., Kang, L.G., Kim, B.Y., Vrtis, R., Roberts, D., Kwong, D.L., IEDM Tech. Digest, p609 (1998).Google Scholar
[7] Ma, Y., Ono, Y., and Hsu, S.T., in MRS Proceedings 567, 31, (1999).Google Scholar
[8] Wilk, G.D. and Wallace, R.M., Appl. Phys. Lett. 74, 2854, 1999; ibid 76, 112, (2000).10.1063/1.124036Google Scholar
[9] Ma, Y., Ono, Y., Stecker, L.S., Evans, D.R., and Hsu, S.T., IEDM Tech. Dig. pp149–152 (1999).Google Scholar
[10] Lee, B., Kang, L., Nieh, R., Qi, Q., and Lee, J. C., Appl. Phys. Lett. 76, 1926, (2000).10.1063/1.126214Google Scholar
[11] Krisch, K.S., Bude, J.D., and Manchanda, L., IEEE Electron Dev. Lett. 17, 521(1996).10.1109/55.541768Google Scholar
[12] Takagi, S., Takayanagi, M., and Toriumi, A., IEEE Trans. Electron Dev. 46, 1446, (1999).10.1109/16.772489Google Scholar
[13] Ma, Y., Evans, D.R., Nguyen, T., Ono, Y., and Hsu, S.T., IEEE EDL 20, 251, (1999).Google Scholar