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The Use of X-ray Topography to Map Mechanical, Thermomechanical and Wire-Bond Strain Fields in Packaged Integrated Circuits

  • Patrick J. McNally (a1), R. Rantamäki (a2), John W. Curley (a1), T. Tuomi (a2), A. N. Danilewsky (a3) and P. A. F. Herbert (a4)...


Thermal processing steps in the production of packaged integrated circuits can lead to thermomechanical stresses. Additionally, the process of bonding wires to contact pads can lead to strain fields attributable to these. Synchrotron x-ray topography has been applied to packaged EEPROM Si ICs in order to produce maps of the strain fields induced by such processing steps. This technique allows for depth-resolved mapping with resolutions currently in the region of 5–10 μm throughout the entire mapping volume.



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