Whereas one-dimensional models can adequately predict the current-voltage behavior of ideal thin-film transistors, a detailed study of current flow requires a comprehensive two-dimensional simulation. Such an analysis provides important information regarding effective series resistance, overlap capacitance, and currentcrowding near electrodes. Numerical simulations also allow the rapid development and optimization of new devices.
We have developed a two-dimensional finite-element device simulator (MANIFEST) which we have used to study the effect of source-to-gate misalignments on the performance of amorphous-silicon TFTs. We find that submicron source-togate gaps do not seriously impair TFT performance.