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Theory of Vertical Amorphous Silicon Thin-Film Transistors

  • J. G. Shaw (a1) and M. Hack (a1)

Abstract

We describe a vertical amorphous silicon thin-film transistor which is easy to fabricate and has a very short channel length that is determined by deposition, not lithography. Our vertical TFTs are compatible with large-area processing techniques andd have suitable terminal characteristics for use in practical circuits. Unlike a conventional thin-film transistor, the current path is primarily parallel to the electric field created by an insulated gate electrode. A two-dimensional computer program is used to analyze these devices and guide their design and optimization. We show how to suppress excessive leakage currents and improve the saturation of the output characteristics by a novel current-blocking technique.

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1) Hack, M., Shaw, J.G., and Shur, M., Mat. Res. Soc. Symp. Proc. 118, 207 (1988).
2) Adler, M.S., in Numerical Analysis of Semiconductor Devices, Browne, B.T. and Miller, J.J. (Eds.), Dublin: Boole Press, 3 (1979).
3) Shaw, J.G. and Hack, M., J. Appl. Phys. 65 (5), 2124 (1989).
4) Shaw, J.G. and Hack, M., Mat. Res. Soc. Symp. Proc. 118, 225 (1988).
5) Shaw, J.G. and Hack, M., J. Appl. Phys. 64 (9), 4562 (1988).
6) Tsang, P., Ogura, S., Walker, W., Shepard, J., and Critchlow, D., IEEE Trans. Elec. Dev. ED–29, 590 (1982).
7) Shur, M. and Hack, M., J. Appl. Phys. 55, 3831 (1984).
8) Tuan, H.C., Mat. Res. Soc. Symp. Proc. 70, 651 (1986).
9) Shur, M. and Hack, M., Mat. Res. Soc. Symp. Proc. 49, 69 (1985).
10) Shaw, J.G. and Hack, M., to be published in J. Appl. Phys. (1989).

Theory of Vertical Amorphous Silicon Thin-Film Transistors

  • J. G. Shaw (a1) and M. Hack (a1)

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