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Stress-Induced Voiding vs Temperature and Passivation Thickness IN Al-0.5%Cu-2%Si, AI-0.5%Cu AND Al-1%Si

  • T. D. Sullivan (a1) and L. A. Miller (a1)

Abstract

Stress-induced voiding in microelectronics chips has been reported to exhibit a variety of dependencies on temperature and on passivation stress. The dependence of line failure is reported here at four different temperatures (150, 225, 285, and 315 ºC) for AI-0.5%Cu and, AI-0.5%Cu and AI-1%Si lines with passivation thicknesses (silicon oxide or silicon nitride) ranging from 0.1 to 2.5 times the metal thickness. Failure distributions change in a complex manner with changing passivation thickness, and with temperature for a specific passivation thickness, raising questions on the validity of using the conventional median time to failure (t 50) and lognormal slope (σ) to project field failure rates from data generated by accelerated life testing.

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Stress-Induced Voiding vs Temperature and Passivation Thickness IN Al-0.5%Cu-2%Si, AI-0.5%Cu AND Al-1%Si

  • T. D. Sullivan (a1) and L. A. Miller (a1)

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