Metal-induced crystallization (MIC) of amorphous Si is gaining increased interest because of its potential use for low-temperature fabrication of integrated circuits. In this work, the MIC technique was used to make Si nanocrystals and the effects of stress on the crystallization were studied. Amorphous Si films were deposited onto the Si substrate with thermal oxides on top by low-pressure chemical vapor deposition (LPCVD) and then patterned into nanoscale pillars by electron beam lithography and reactive ion etching. A conformal low-temperature oxide (LTO) layer was deposited to cover the pillars, followed by an anisotropic etch back to form a spacer, leaving only the top surface of the pillars exposed to the 5 nm Ni sputtering deposition afterwards. An HF dip was used to partially remove the LTO spacers on the pillars, leading to different LTO thicknesses on different samples. These samples were then annealed to crystallize the amorphous Si pillars, forming Si nanocrystals. Transmission electron microscope (TEM) observations after anneal found a clear dependence of the crystallization rate on the pillar size as well as the LTO thickness. The crystallization rate was lower for pillars with thicker LTO spacers, while for the same LTO thickness the crystallization rate was lower for pillars with narrower width. A model based on the stress in the pillars is proposed to explain this dependence. This model suggests some methods to control the nickel-induced crystallization process and achieve higher quality Si nanocrystals.