Hostname: page-component-8448b6f56d-c4f8m Total loading time: 0 Render date: 2024-04-20T02:09:12.774Z Has data issue: false hasContentIssue false
  • English
  • Français

Simulation of Wiring Capacitance For Sub-Quarter-Micron Ulsi Devices and Its Application

Published online by Cambridge University Press:  10 February 2011

T. Hasegawa ,
T. Kobayashi ,
S. Kadomura  and
J. Aoyama
T. Hasegawa
Affiliation:
ULSI R&D Laboratories, Semiconductor Company, Sony Corporation 4-14-1 Asahi-cho, Atsugi, Kanagawa, 243, Japan Tel. +81 462(30)5373 FAX +81 462(30)5730
T. Kobayashi
Affiliation:
ULSI R&D Laboratories, Semiconductor Company, Sony Corporation 4-14-1 Asahi-cho, Atsugi, Kanagawa, 243, Japan Tel. +81 462(30)5373 FAX +81 462(30)5730
S. Kadomura
Affiliation:
ULSI R&D Laboratories, Semiconductor Company, Sony Corporation 4-14-1 Asahi-cho, Atsugi, Kanagawa, 243, Japan Tel. +81 462(30)5373 FAX +81 462(30)5730
J. Aoyama
Affiliation:
ULSI R&D Laboratories, Semiconductor Company, Sony Corporation 4-14-1 Asahi-cho, Atsugi, Kanagawa, 243, Japan Tel. +81 462(30)5373 FAX +81 462(30)5730
Get access

Abstract

Wiring capacitance in a multilevel interconnecting structure for sub-quarter-micron ULSI devices has been studied using a simulator called SENECA1), which is developed by the Technical University of Vienna and Sony corporation, for optimizing the structure with low dielectric constant materials as interlevel dielectric layers. The simulation results suggest that an optimized structure model should have an ILD(Inter-Level Dielectrics) thickness of 0.7μm and a metal thickness of 0.4μm for sub-quarter-micron ULSI devices. The application of the low dielectric constant materials to the ULSI devices is examined and also discussed with focusing on feasibility and reliability issues. Calculated wiring capacitance is compared with actual capacitance based on the optimized structure. The 33.2% reduction of capacitance is obtained with using an organic film with dielectric constant of 2.4 in excellent accordance with the simulation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 446: Amorphous and Crystalline Insulating Thin Films–1996 , 1996 , 227
Copyright
Copyright © Materials Research Society 1997

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1 Mukai, M., Tatsumi, T., Nakauchi, N., Kobayashi, T., Koyama, K., Komatsu, Y., Bauer, R., Rieger, G. and Selberherr, S., 1995 6th International Conference on Simulation of Semiconductor Device and Process (SISDEP ‘95), pp. 151 (1995).Google Scholar
2 Hasegawa, T., Kobayashi, T., Kadomura, S., and Aoyama, J., 1995 Dielectrics for ULSI Multilevel Interconnection Conference (DUMIC), pp. 197 (1995).Google Scholar
3 Ichikawa, M., Inoue, K., Izumi, K., Sato, S., Mitarai, S., Kai, M., and Watanabe, K., 1995 VLSI Multilevel Interconnection Conference (VMIC), pp. 254 (1995).Google Scholar
4 Furusawa, T., Homma, Y., Shimamura, Y., Morishima, H., Yamamoto, Y. and Satoh, H., Proc. VMIC, Santa Clara, pp. 186–192 (1994).Google Scholar