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Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects

  • Kwanho Yang (a1), Joost J. Waeterloos (a1), Jang-Hi Im (a1) and Michael E. Mills (a1)

Abstract

The thermomechanical reliability of Cu/low-k interconnects, which is directly related to yield problems and premature device failures, has been a major issue. The development of a manufacturing process, which can satisfy the most stringent reliability standards, requires detailed information on the thermomechanical behavior of Cu/low-k interconnects. The thermomechanical behavior of Cu/low-k interconnects is complicated by the fact that processinduced thermal stresses are developed during the manufacturing process. A conventional finite element analysis (FEA) approach has some difficulties to model Cu/low-k interconnects that keep changing during process steps. Therefore, a sequential process modeling technique has been developed to simulate the interconnect behavior to substantially any level of detail and understand the complex thermomechanical behavior of Cu/low-k interconnects while being manufactured. In this paper, we briefly describe a sequential process modeling technique and demonstrate how we use the modeling technique to solve a Cu/SiC delamination problem in a Cu/SiLK* semiconductor dielectric dual damascene test structure.

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[1] http://ublic.itrs.net/
[2] Gan, D., Wang, G., Ho, P.S., Morrow, X. and Leu, J., Proc. Int. Interconnect Tech. Conf. 2002, pp. 271273.
[3] Mercado, L., Goldberg, C., Kuo, S., Proc. Int. Interconnect Tech. Conf. 2002, pp. 119121.
[4] Gonda, V., Toonder, J.M.J. Den, Beijer, J., Zhang, G.Q., Hoofman, R.J.O.M., Ernst, L.J., Proc. Of EuroSIME 2003, pp. 359363.

Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects

  • Kwanho Yang (a1), Joost J. Waeterloos (a1), Jang-Hi Im (a1) and Michael E. Mills (a1)

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