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RTA Processing of W-Polycide Dual-Gate Sub-Micron Structures for Low-Voltage CMOS Technology

  • J. Bevk (a1), M. Furtsch (a1), G. E. Georgiou (a1), S. J. Hillenius (a1), D. Schielein (a1), T. Schiml (a1), P. J. Silverman (a1) and H. S. Luftman (a1)...

Abstract

Deep submicron CMOS technology for low-power, low-voltage applications requires the use of symmetric n+/p+ poly gate structures. This requirement introduces a number of processing challenges, involving fundamental issues of atomic diffusion over distances of 1Å to ∼30μm. Two of the critical issues are dopant cross-diffusion between P- and NMOS devices with connected gates, resulting in large threshold voltage shifts, and boron penetration through the gate oxide. We show that in devices with W-polycide dual-gat:e structure most of these problems can be alleviated by using rapid thermal annealing, RTA, in combination with a few additional, simple processing steps (e. g., low-temperature recrystallization of a-Si layer and selective nitrogen coimplants). The RTA step, in particular, ensures thai: the boron activation in the p+ poly-Si remains high and negates any effects of arsenic cross-diffusion. CMOS devices with properly processed gates have low gate stack profiles, small threshold voltage shifts (<30mV), and excellent device characteristics.

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1. Bevk, J., Georgiou, G. E., Frei, M., Silverman, P. J., Lloyd, E. J., Kim, Y., Luftman, H. S., Furtsch, M., Schiml, T., and Hillenius, S. J., 1995 IEDM Tech. Dig., pp. 893896 and refs. therein.
2. Hayashida, H., Toyoshima, Y., Suizu, Y., Mitsuhashi, K., Iwai, H., and Maeguchi, K., Symp. on VLSI Tech., pp. 2930, 1989.
3. Bevk, J. et al. , to be published.
4. Schiml, T., Bevk, J., Furtsch, M., Georgiou, G. E., Cirelli, R., Mansfield, W. M., Silverman, P. J., and Luftman, H. S., these Proceedings.
5. Krisch, K. S., Bude, J., and Manchanda, L., Proceedings of the Symposium on Diagnostic Techniques for Semiconductor Materials and Devices (Electrochemical Society, 1994), pp. 1223.

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RTA Processing of W-Polycide Dual-Gate Sub-Micron Structures for Low-Voltage CMOS Technology

  • J. Bevk (a1), M. Furtsch (a1), G. E. Georgiou (a1), S. J. Hillenius (a1), D. Schielein (a1), T. Schiml (a1), P. J. Silverman (a1) and H. S. Luftman (a1)...

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