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Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing

  • Takeo Matsuki (a1), Yasushi Akasaka (a1), Kiyoshi Hayashi (a1), Masataka Noguchi (a1), Koji Yamashita (a1), Hideyuki Syoji (a1), Kazuyoshi Torii (a1), Naoki Kasai (a1) and Tsunetoshi Arikado (a1)...


A Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.



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