As design rules shrink to conform with ULSI device dimensions, gate dielectrics for MOSFET structures are required to be scaled to even thinner proportions. Upon scaling the gate oxides below ∼60Å the interfacial region becomes a significant proportion of the total film. Thus interface properties are weighted more heavily in determining device performance and reliability.
We have developed a Pump-Probe charge integrating measurement technique for studying the emission kinetics of traps in the M/SiO2/Si system. Essentially, a MOS capacitor is pumped by exposure to a charging pulse. The emission of the charge at short time scales (<10ms), can be measured using a delayed application of a probe pulse which determines the remainder of the filled traps as a function of delay time. For a lightly doped p-Si (lll) substrate, we observe an uncommon behavior of the emission kinetics in the initial time regime (< 100ms). A possible explanation for this phenomenon is the perturbation of the emission cross-section of the probed traps due to the presence of another state in communication with the trap site.