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Processing of Ferroelectric Memories

Published online by Cambridge University Press:  15 February 2011

Carlos A. Paz De Araujo ,
L. D. McMillan  and
J. F. Scott
Carlos A. Paz De Araujo
Affiliation:
Symetrix Corporation, Colorado Springs, CO 80918 and The University of Colorado, Depts. of Physics and of Electrical Engineering and Computer Engineering, Boulder, CO 80309-0390 and Colorado Springs, CO 80933-7150
L. D. McMillan
Affiliation:
Symetrix Corporation, Colorado Springs, CO 80918 and The University of Colorado, Depts. of Physics and of Electrical Engineering and Computer Engineering, Boulder, CO 80309-0390 and Colorado Springs, CO 80933-7150
J. F. Scott
Affiliation:
Symetrix Corporation, Colorado Springs, CO 80918 and The University of Colorado, Depts. of Physics and of Electrical Engineering and Computer Engineering, Boulder, CO 80309-0390 and Colorado Springs, CO 80933-7150
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Abstract

This paper describes the classification of existing integration schemes for ferroelectric memories, including both nonvolatile and volatile devices, and the status of device development for CMOS (both SRAM and DRAM architecture), GaAs JFET structures, bipolar, and true ferroelectric FETs (in which the ferroelectric is deposited in the gate region to modify the source-to-drain current when the polarization is reversed). Emphasis in the paper is on electroding, film deposition, drying and baking, and annealing steps.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 230: Symposium R – Phase Transformation Kinetics in Thin Films , 1991 , 277
Copyright
Copyright © Materials Research Society 1992

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References

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