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Process and Manufacturing Challenges for High-K Gate Stack Systems

Published online by Cambridge University Press:  10 February 2011

M.C. Gilmer ,
T-Y Luo ,
H.R. Huff ,
M.D. Jackson ,
S. Kim ,
G. Bersuker ,
P. Zeitzoff ,
L. Vishnubhotla ,
G.A. Brown  and
R. Amos
...Show all authors
M.C. Gilmer
Affiliation:
SEMATECH, Austin, TX. 78741
T-Y Luo
Affiliation:
SEMATECH, Austin, TX. 78741
H.R. Huff
Affiliation:
SEMATECH, Austin, TX. 78741
M.D. Jackson
Affiliation:
SEMATECH, Austin, TX. 78741
S. Kim
Affiliation:
SEMATECH, Austin, TX. 78741
G. Bersuker
Affiliation:
SEMATECH, Austin, TX. 78741
P. Zeitzoff
Affiliation:
SEMATECH, Austin, TX. 78741
L. Vishnubhotla
Affiliation:
SEMATECH, Austin, TX. 78741
G.A. Brown
Affiliation:
SEMATECH, Austin, TX. 78741
R. Amos
Affiliation:
SEMATECH, Austin, TX. 78741
D. Brady
Affiliation:
SEMATECH, Austin, TX. 78741
V.H.C. Watt
Affiliation:
SEMATECH, Austin, TX. 78741
G. Gale
Affiliation:
SEMATECH, Austin, TX. 78741
J. Guan
Affiliation:
SEMATECH, Austin, TX. 78741
B. Nguyen
Affiliation:
SEMATECH, Austin, TX. 78741
G. Williamson
Affiliation:
SEMATECH, Austin, TX. 78741
P. Lysaght
Affiliation:
SEMATECH, Austin, TX. 78741
K. Torres
Affiliation:
SEMATECH, Austin, TX. 78741
F. Geyling
Affiliation:
SEMATECH, Austin, TX. 78741
C.F.H. Gondran
Affiliation:
SEMATECH, Austin, TX. 78741
J. A. Fair
Affiliation:
Novellus Corporation, San Jose, CA 95134
M.T. Schulberg
Affiliation:
Novellus Corporation, San Jose, CA 95134
T. Tamagawa
Affiliation:
Jet Process Corporation, New Haven, CT 06511
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Abstract

A design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 567: Symposium R – Ultrathin SiO2 and Higg-K Materials for ULSI Gate Dielectrics , 1999 , 323
Copyright
Copyright © Materials Research Society 1999

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References

REFERENCES

1 Dennard, R.H., Gaensslen, F.H., Yu, H.-N., Rideout, V.L., Bassous, E. and LeBlanc, A.R., “Design of Ion-Implanted MOSFET's With Very Small Physical Dimensions,” IEEE J. Solid-State Circuits, SC–9, 256–268 (1974)10.1109/JSSC.1974.1050511Google Scholar
2 Dennard, R.H., “Scaling Challenges for DRAM and Microprocessors in The 21st Century,” ULSI Science and Technology/1997, (edited by Massoud, H.Z., Iwai, H., Claeys, C. and Fair, R.B.), 519–532 (1997), The Electrochemical Society, Inc., Pennington, N.J. Google Scholar
3 Moore, G.E., “Cramming More Components Onto Integrated Circuits,” Electronics, 38, No. 8., 114–117 (1965)Google Scholar
4 Moore, G.E., “Progress in Digital Integrated Electronics,” IEDM, 11–13 (1975)Google Scholar
5 Moore, G.E., “Lithography and The Future of Moore's Law,” SPIE 2438, 2–17 (1995)Google Scholar
6 Lo, S.-H., Buchanan, D.A., Taur, Y. and Wang, W., “Quantum-Mechanical Modeling of Electron Tunneling Current From The Inversion Layer of Ultra-Thin-Oxide nMOSFET's,” IEEE Electron Device Lett., 18, 209–211 (1997)10.1109/55.568766Google Scholar
7 SIA 1997 Roadmap, Semiconductor Industry Association, 181 Metro Drive, Suite 450, San Jose, CA 95110Google Scholar
8 Frank, D.J., Taur, Y. and Wong, H-S. P, “Generalized Scale Length for Two-Dimensional Effects in MOSFET's,” IEEE Electron Device Letters, 19, 385–387 (1998)10.1109/55.720194Google Scholar
9 Chatterjee, A, Chapman, R.A., Dixit, G., Kuehne, J., Hattangady, S., Yang, H., Brown, G.A., Aggarwal, R., Erdogan, U., He, Q., Hanratty, M., Rogers, D., Murtaza, S., Fang, S.J., Rotondaro, A.L.P., Hu, J.C., Terry, M., Lee, W., Fernando, C., Konecni, A., Wells, G., Frystak, D., Bowen, C., Rodder, M. and Chen, I.-C., “Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process,” IEDM 821–824 (1997)Google Scholar
10 Chatterjee, A., Chapman, R.A., Joyner, K., Otobe, M., Hattangady, S., Bevan, M., Brown, G.A., Yang, H., He, Q., Rogers, D., Fang, S.J., Kraft, R., Rotondaro, A.L.P., Terry, M., Brenna, K., Aur, S.-W., Hu, J.C., Tsai, H-L, Jones, P., Wilk, G., Aoki, M., Rodder, M. and Chen, I.-C., “CMOS Metal Replacement Gate Transistors using Tantalum Pentoxide Gate Insulator,” IEDM 777–780 (1998)Google Scholar
11 Bersuker, G., Zeitzoff, P., Vishnubhotla, L., Huff, H.R., Brady, D., Gilmer, M., Jackson, M.D, Torres, K., Nguyen, B., Kim, S., Williamson, G., Guan, J. and Lysaght, P., Replacement Gate Process for High-K CMOS Transistors, ECS Ext. Abst., 99-1, Abst. No. 165 (1999)Google Scholar
12 Hubbard, K.J. and Schlom, D.G., “Thermodynamic Stability of Binary Oxides in Contact With Silicon,” J. Mater. Res., 11, 2757–2776 (1996)10.1557/JMR.1996.0350Google Scholar
13 Vogel, E. M. and Wortman, J. J., “Properties of N- and P-Channel MOSFETs with Ultrathin RTCVD Oxynitride Gate Dielectrics,” Fifth International Symposium on Silicon Nitride and Silicon Dioxide Thin Insulating Films (edited by Sundaram, K.B., Deen, M.J., Brown, W.D., Sah, R.E., Poindexter, E., Misra, D., Allendorf, M.D. and Raider, S.I.) (1999), ECS, (to be published), see also ECS Ext. Abst., 99-1, Abst No. 130 (1999)Google Scholar
14 Harrison, H.B., LI, H.-F., Dimitrijev, S. and Tanner, P., “Nitrogen in Ultra Thin Dielectrics, Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices” (edited by Garfunkel, E., Gusev, E. and Vul', A.,) NATO Science Series, 47, 191–215 (1998)Google Scholar
15 Ma, T.P., “Making Silicon Nitride Film a Viable Gate Dielectric,” IEEE Trans. Electron Dev., 45, 680–690 (1998)10.1109/16.661229Google Scholar
16 Ma, T.P., private communication, June 22, 1999 Google Scholar
17 Yamamoto, K. and Nakazawa, M., “Studies of NH3 Thermal Nitridation of Ultrathin Si-Oxide Films on Si Using Photoemission Spectroscopy with Synchrotron Radiation,” Jpn. J. Appl.Phys., 33, 285–289 (1994)10.1143/JJAP.33.285Google Scholar
18 Liu, C.T., Lloyd, E.J., Ma, Y., Du, M., Opila, R.L. and Hillenius, S., “High Performance 0.2 μtm CMOS with 25 Å Gate Oxide Grown on Nitrogen Implanted Si Substrates,” IEDM, 499–502 (1996)Google Scholar
19 Chen, Y.Y., Liu, I.M., Gardner, M., Fulford, J. and Kwong, D.L., “Performance and Reliability Assessment of Dual-Gate CMOS Devices with Gate Oxide Grown on Nitrogen Implanted Si Substrates,” IEDM, 639–642 (1997)Google Scholar
20 Lysaght, P.S., Nguyen, B., Bennett, J., Willliamson, G., Torres, K., Gilmer, M., Luo, T-Y, Brady, D., Guan, J., Brown, G.A., Zeitzoff, P., Bersuker, G., Geyling, F., Gebara, G., Vishnubhotla, L., Jackson, M.D. and Huff, H.R., “Experimental Observations of The Redistribution of Implanted Nitrogen at The Si-SiO2 Interface During RTA Processing, Silicon Front-End Processing—Physics and Technology of Dopant-Defect Interactions,” (edited by Gossmann, H-J, Haynes, T., Larsen, A.R. and Law, M.) (1999) MRS Proceedings, (to be published)10.1557/PROC-568-283Google Scholar
21 Lucovsky, G., “Spatially-Selective Incorporation of Bonded-Nitrogen Into Ultra-Thin Gate Dielectrics by Low-Temperature Plasma-Assisted Processing, Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices,” (edited by Garfunkel, E., Gusev, E. and Vul', A.,) NATO Science Series, 47, 147–164 (1998)Google Scholar
22 Summerfelt, S.R., “(Ba,Sr)TiO3 Thin Films For DRAM's,” Thin Film Ferroelectric Materials and Devices (edited by Ramesh, R.) 1-42, Kluwer Academic Publishers (1997)Google Scholar
23 Mikami, N., “(Ba,Sr) TiO3 Films and Process Integration For DRAM Capacitor,” Thin Film Ferroelectric Materials and Devices (edited by Ramesh, R.) 43-70, Kluwer Academic Publishers (1997)Google Scholar
24 Crenshaw, D.L., Gupta, I.J., Lin, B.Y., Plumton, D., Bevan, M., Banerjee, A., Wise, R. and Horner, G.S., “Time Efficient Corona Discharge Methods for Making Capacitance Measurements for High-Density DRAM Materials,” Semiconductor Silicon/1998, (edited by Huff, H.R., Gosele, U. and Tsuya, H.), 1610–1620 (1998)Google Scholar
25 Gray, P.V., “The Silicon-Silicon Dioxide System, Proc.” IEEE, 57, 1543–1551 (1969)10.1109/PROC.1969.7334Google Scholar
26 Hauser, J.R. and Ahmed, K., Characterization of Ultra-Thin Oxides Using Electrical C-V and I-V Measurements, Characterization and Metrology for ULSI Technology: 1998 International Conference (edited by Seiler, D., Diebold, A.C., Bullis, W.M., Shaffner, T.J., McDonald, R. and Walters, E.J.), 235–240 (1998)10.1063/1.56801Google Scholar
27 Lo, S-H, Buchanan, D. and Taur, Y., “Modeling and Characterization of Quantization, Polysilicon Depletion and Direct Tunneling Effects in MOSFET's with Ultrathin Oxides,”. IBM J. Res. and Develop., 43, 327–337 (1999)10.1147/rd.433.0327Google Scholar
28 Szweda, R., “Annealing Effects in Silicon Nitride Encapsultant Films,” Physica B&C, 129B+C, 435–439 (1985)Google Scholar
29 Seki, S., Unagami, T., Tsujiyama, B., “Electrical Characteristics of RF Magnetron-Sputtered Tantalum Pentoxide Silicon Interface,” J. Electrochemical Soc., 131, 2621–2625 (1984)10.1149/1.2115371Google Scholar
30 Ito, T., Ishikawa, H. and Nakamura, T., Thin Film Technology of VLSIs, Maruzen, Tokyo (1986), Chapter 4 (in Japanese)Google Scholar
31 Alers, G. B., Stirling, L.A., VanDover, R.B., Chang, J.P., Werder, D.J., Urdahl, R. and Rajopalan, R., “Effect of Thermal Stability and Roughness on Electrical Properties of Tantalum Oxide Gates,” Ultrathin SiO2 and High-K Materials for ULSi Gate Dielectrics (edited by Huff, H. R., Richter, C. A., Green, M. L., Lucovsky, G. and Hattori, T.), MRS Proceedings 567, 391–396 (1999).Google Scholar
32 Saks, N. S., Ma, D.I. and Fowler, W.B., “Nitrogen Depletion During Oxidation in N2O,” Appl. Phys. Lett., 67, 374–376 (1995)10.1063/1.114633Google Scholar
33 Garfunkel, E., private communication, May 6, 1999 Google Scholar
34 Kooi, E., “The Invention of LOCOS,” IEEE Case Histories of Achievement in Science and Technology, 1, Institute of Electrical and Electronics Engineers, Inc.,(1991)Google Scholar
35 Matsuhashi, H. and Nishikawa, S., “Optimum Electrode Materials for Ta2O5 Capacitors for High- and Low-Temperature Processes,” Jpn. J. Appl. Phys. 33, 1293–1297 (1994)10.1143/JJAP.33.1293Google Scholar
36 Misra, V. and Lucovsky, G., “Alternative Gate Electrode Materials,” SRC/SEMATECH Research Center Presentation, Sept. 16-17,1998 Google Scholar
37 Taur, Y. and Ning, T.H., Fundamentals of Modern VLSI Devices, Cambridge University Press (1998)Google Scholar
38 Alers, G.B., Werder, D.J., Chabal, Y., Lu, H.C., Gusev, E.P., Garfunkel, E., Gustafson, T. and Urdahl, R.S., “Intermixing at the Tantalum Oxide/Silicon Interface in Gate Dielectric Structures,” Appl.Phys. Lett., 73, 1517–1519 (1998)10.1063/1.122191Google Scholar