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Pre-applied Inter Chip Fill Material and Process for Advanced 3D Chip Stack

Published online by Cambridge University Press:  31 January 2011

Akihiro Horibe  and
Fumiaki Yamada
Akihiro Horibe
Affiliation:
hory@jp.ibm.com, Association of Super-Advanced Electronics Technologies (ASET), Tokyo, Japan
Fumiaki Yamada
Affiliation:
hory@jp.ibm.com, Association of Super-Advanced Electronics Technologies (ASET), Tokyo, Japan
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Abstract

To pursue further performance improvement of semiconductor devices, threedimensional (3D) chip integration with TSV would be one of the key technologies in the next decade. Inter Chip Fill (ICF) is a resin to fill gaps between chips, and it would be an important component for highly reliable and durable 3D integrated devices. High performance 3D devices require fine pitch interconnections with small bumps for high pin count with high bandwidth. Smaller bumps lead to narrow gap design between stacked chips inevitably, and the narrow gap is expected to reduce heat resistance and thermo-mechanical stress. However it makes resin filling and flux cleaning processes harder. A preapplied ICF process is one of the potential methods to fill the narrow gaps with a resin. The material is halfcured resin applied on a wafer by spin-coating or film-lamination before chip integration. Flux cleaning process can be eliminated by adding fluxing function in the resin components. Major concerns of multiple chip 3D stacking process are repeated high temperature cycles of metal-joining, and long process time as a result. We are proposing “Stack Joining process” that enables 3D multi chip joining at one time instead of sequential chip by chip joining. In this process, multiple chips are aligned and temporarily stacked sequentially using adhesivity which the ICF has between Tg and initiation temperature of polymerization, and finally all metal bumps of stacked chips are melted and joined altogether. This process can substantially reduces repeated high temperature cycles and process time. As a result this technique could mitigate degradation of device materials.

We successfully stacked chips by using the pre-applied ICF which was designed for advanced 3D chip stack having full area array and narrow gap (less than 10um) connections. In this paper, we explain the Stack Joining process flow and conditions. We also discuss the cause of mechanical stress within the stacked chip and required material features of the pre-applied ICF and device structure to reduce the stress.

Keywords

packagingelectronic materialinsulator
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1195: Symposium B – Rellliability and Materials Issues of Semiconductor Optical and Electrical Devices and Materials , 2009 , 1195-B13-05
Copyright
Copyright © Materials Research Society 2010

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References

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[4] Horibe, Akihiro, Yamada, Fumiaki, “Inter Chip Fill for 3D Chip Stack”, ICEP2009 proceeding (2009)10.5104/jiepeng.2.160Google Scholar
[5] Feger, Claudius, et al., “The Over-Bump Applied Resin Wafer-Level Underfill Process: Process, Material and Reliability” ECTC 2009, pp.1502, (2009)Google Scholar