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Post-Annealing Effect on the Reliability of Ultra-Thin Silicon Dioxide with Polysilicon Gate

  • Kenji Yoneda (a1), Yoshiki Fukuzaki (a1), Kazuo Satoh (a1), Yoshjhiro Todokoro (a1) and Morio Inoue (a1)...

Abstract

Time dependent dielectric breakdown (TDDB) characteristics and TEM observation of ultra-thin silicon dioxide with the polysilicon gate after post-annealing and oxidation at 1000-1100 °C are discussed. The high temperature post-annealing decreases the TDDB characteristics of ultra-thin oxide with polysilicon gate. The charge to breakdown is reduced drastically with increasing the annealing temperature and annealing time. The dielectric breakdown reliability degradation of ultra-thin tunneling oxide by the post-annealing can be explained as the partial oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/ultra-thin tunneling oxide interface. This increase of roughness is due to the grain growth of polysilicon gate and viscous flow of oxide, which are enhanced with increasing the annealing temperature and time.

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(2)Hokari, Y., VLSI Symp. Tech. Dig., p. 41 (1988)
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Post-Annealing Effect on the Reliability of Ultra-Thin Silicon Dioxide with Polysilicon Gate

  • Kenji Yoneda (a1), Yoshiki Fukuzaki (a1), Kazuo Satoh (a1), Yoshjhiro Todokoro (a1) and Morio Inoue (a1)...

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