one method of reducing the area occupied by a RAM cell is to stack the p- and n-channel devices on top of one another. This “stacked CMOS” structure is a first step towards three dimensional integration. The simplest approach is to use polysilicon as the substrate for the top transistors. This paper describes the results of grain growth studies of samples annealed by rapid isothermal annealing. The temperature varied from 1100 to 1400°C and the anneal time varied from 10 to 480 seconds. TEM was used to examine the microstructure of the material. The grain growth was found to be film thickness limited, i.e. the final grain size was approximately the same as the initial film thickness. As a result, the kinetics of grain growth cannot be described by a simple logarithmic time law. There also is a velocity dependent drag contribution to the growth kinetics that implies impurities play an important role. The interlevel oxide thickness affects grain growth. Thicker oxides lead to faster growth, probably by reducing the heat flow to the silicon substrate. A capping layer was found to have no effect on the grain size. The above results indicate that it is possible to obtain large grains in short times using isothermal annealing. This process may be useful for fabricating stacked polysilicon layers in three-dimensional integrated circuits.