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Performance of Poly-Si Tfts with Double Gate Oxide Layers

Published online by Cambridge University Press:  10 February 2011

Byung-Hyuk Min ,
Cheol-Min Park ,
Jae-Hong Jun ,
Byung-Sung Bae  and
Min-Koo Han
Byung-Hyuk Min
Affiliation:
Department of Electrical Engineering., Seoul National Univ., Seoul, 151-742, Korea
Cheol-Min Park
Affiliation:
Department of Electrical Engineering., Seoul National Univ., Seoul, 151-742, Korea
Jae-Hong Jun
Affiliation:
Department of Electrical Engineering., Seoul National Univ., Seoul, 151-742, Korea
Byung-Sung Bae
Affiliation:
Samsung Electronics Co., Kiheung, Yongln-Goon, KyungKi-Do, 449-900, Korea
Min-Koo Han
Affiliation:
Department of Electrical Engineering., Seoul National Univ., Seoul, 151-742, Korea
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Abstract

We have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 424: Symposium H – Flat Panel Display Materials II , 1996 , 171
Copyright
Copyright © Materials Research Society 1997

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