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Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors
Published online by Cambridge University Press: 11 April 2013
Abstract
Accumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges.
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- Information
- MRS Online Proceedings Library (OPL) , Volume 1510: Symposium DD – Group IV Semiconductor Nanostructures and Applications , 2013 , mrsf12-1510-dd05-20
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- Copyright © Materials Research Society 2013